Packet transmitter

ABSTRACT

There is disclosed a packet transmission apparatus for transmitting in a packet form a transmission unit including a data string arranged so as to divide predetermined data into a plurality of blocks, each block having a fixed length, block information for specifying the block type being added to each block. A DIF data processing circuit generates a transmission header having a new identifier by deleting predetermined redundancy information from the block information belonging to the plurality of blocks based on inputted data string, and then, generates a transmission unit having the generated transmission header. Next, a transmission terminal unit transmits the generated transmission unit by way of a transmission line. In this case, the DIF data processing circuit generates a new identifier by making the information of one block represent the information of the plurality of blocks to generate a transmission header having the generated identifier, or making the information of one block represent the information of an identical block or deleting the redundancy information including at least one of reserved data and invalid data.

TECHNICAL FIELD

The present invention relates to a packet transmission apparatus fortransmitting compressed coded image data, audio data and additionalinformation data or general data in a packet form by way of atransmission line.

BACKGROUND ART

In recent years, the capacity of communications has remarkably increasedaccording to development of communications systems utilizing opticalfiber cables and the like, and digital transmission systems fortransmitting not only digital data for use in computers and the like,but also, for example, an image signal, an audio signal and the otheradditional information after being digitized has been put into practicaluse.

For example, use of an asynchronous transfer mode (referred to as an ATMhereinafter) or the like enables transmission at a rate of not lowerthan 155 megabits per second, and an ATM transmission system fortransmitting image data by way of an ATM transmission line has been putinto practical use.

In regard to the ATM transmission system, there is providedstandardization through discussions by ITU-T (InternationalTelecommunication Union-Telecommunication Standardization Sector), TheATM Forum and so forth, and many relevant documents have been published.

For example, a prior art for communicating a video signal in a packetform is disclosed in the prior art reference of U.S. Pat. No. 5,159,452(referred to as a prior art hereinafter).

In the prior art, an example in which a packet loss position (packetloss information) is known and loss correction is executed is shown inFIGS. 6A and 6B of the prior art, and an example in which errorcorrection is executed is shown in FIG. 7 of the prior art.

However, the prior art construction as described above has had thefollowing problems.

(1) When handling communications in, for example, the ATM, transmissionis executed in a unit of packet of 53 bytes called a cell. If a packetloss (cell loss) occurs, then the cell is lost within the ATM network,and therefore, this leads to such a problem that the occurrence of thecell loss within the ATM network cannot be detected from the informationof the cell itself received by a reception terminal. As is natural forthe above reasons, there has been such a problem that the position inwhich the cell loss has occurred cannot be identified. Therefore, theloss correction that must essentially identify the position of the error(cell loss) is impossible unless a special constituent factor forinforming the reception terminal of the occurrence of the cell loss fromthe network side is provided. provided.

(2) Although the identification of the error position and correction areenabled by using the error correction method shown in FIG. 7 of theprior art, the method has had such a problem that the efficiency is lowwhen the error correction is executed in terms of the number of errorsthat can be corrected with respect to the parity amount for errorcorrection use to be added, i.e., the total amount of transmission andthe number of error corrections (error correcting performance).

There has been such a further problem that the probability of theoccurrence of cell loss disadvantageously increases due to thecongestion of the ATM network when the total amount of transmissionincreases.

(3) In the ATM, an ATM adaptation layer (referred to as an AALhereinafter) is prescribed by the standard of ITU-T Recommendation, andthere are many types of equipment that cope with the standard. However,the prior art, which does not use the universal AAL function, has hadsuch a problem that, for example, the error detection of the AAL type 5cannot be utilized. It is also essential to independently input, forexample, the function that a signal representing the breakpoint of asequence of a video signal must be independently inputted, for which thetransmission efficiency is low and no universal equipment can be used,and this leads to such a problem that no interconnecting capabilityexists.

There has also been such a problem that the processing circuit scale islarge, and a cost is very high since no universal equipment can be used.

A first object of the present invention is to provide a packettransmission apparatus capable of enabling transmission toleratingpacket loss (cell loss) by reducing the probability of the occurrence ofthe packet loss (cell loss) and improving the reliability of real-timecommunications.

A second object of the present invention is to provide a packettransmission apparatus capable of effectively utilizing a communicationszone, enabling the ATM layers to be utilized from upper layers andeasily using the currently popularized or prevailed ATM equipments.

A third object of the present invention is to provide a packettransmission apparatus capable of improving the error correctionefficiency and error correction capability with respect to the amount ofparity added by executing error correction or error detection, enablingthe ATM layers to be utilized from upper layers and easily using thecurrently popularized ATM equipments.

Furthermore, a fourth object of the present invention is to provide apacket transmission apparatus that has a simpler apparatus constructionand is less expensive as compared with the prior art.

DISCLOSURE OF THE INVENTION

According to the first aspect of the present invention, there isprovided a packet transmission apparatus for transmitting in a packetform a transmission unit including a data string arranged so as todivide predetermined data into a plurality of blocks, each block havinga fixed length, wherein block information for specifying a block type isadded to each block. The packet transmission apparatus according to thefirst aspect of the present invention comprises generating means forgenerating a transmission header having a new identifier by deletingpredetermined redundancy information from the block informationbelonging to the plurality of blocks based on said data string, andgenerating a transmission unit having the generated transmission header,and transmitting means for transmitting the transmission unit generatedby said generating means by way of a transmission line.

generating means for generating a transmission header having a newidentifier by deleting predetermined redundancy information from theblock information belonging to the plurality of blocks based on saiddata string, and generating a transmission unit having the generatedtransmission header; and

transmitting means for transmitting the transmission unit generated bysaid generating means by way of a transmission line.

Also, in the above-mentioned packet transmission apparatus, thegenerating means preferably generates a new identifier by making theinformation of one block represent the information of the plurality ofblocks, and generates a transmission header having the generatedidentifier.

Further, in the above-mentioned packet transmission apparatus, thegenerating means preferably makes the information of one block representthe information of an identical block.

Furthermore, in the above-mentioned packet transmission apparatus, thegenerating means preferably deletes the redundancy information includingat least one of reserved data and invalid data.

Also, in the above-mentioned packet transmission apparatus, thetransmission header preferably includes a time code and a serial number.

Further, in the above-mentioned packet transmission apparatus, thetransmitting means preferably transmits the transmission unit by an ATMtransmission system using the AAL TYPE 1 as an adaptation layer functionof an asynchronous transfer mode.

Furthermore, in the above-mentioned packet transmission apparatus, thetransmitting means preferably transmits the transmission unit by an ATMtransmission system using the AAL TYPE 5 as an adaptation layer functionof an asynchronous transfer mode.

Also, in the above-mentioned packet transmission apparatus, thetransmitting means preferably adds a parity for error correction to thegenerated transmission unit, thereafter, executes an interleave processon data including the added parity for error correction, and outputsdata obtained after the interleave process as a transmission unit.

Further, in the above-mentioned packet transmission apparatus, thegenerating means preferably executes the interleave process by writingthe data including the added parity for error correction into a storageapparatus having a matrix form in a first direction of the matrix, andthereafter, reading from the storage apparatus the data in a seconddirection perpendicular to the first direction of the matrix.

According to the second aspect of the present invention, there isprovided a packet transmission apparatus for transmitting in a packetform a transmission unit including a data string arranged so as todivide predetermined data into a plurality of blocks, wherein each blockhas a fixed length. The packet transmission apparatus according to thesecond aspect of the present invention comprises a first interleaveprocessing means for executing a first interleave process by writing thedata string into a first storage apparatus having a first matrix form ina first direction of the first matrix, and thereafter, reading from thefirst storage apparatus the data in a second direction perpendicular tothe first direction of the first matrix, and for outputting the dataobtained after the first interleave process in a unit of data in thesecond direction, parity adding means for adding a predetermined parityfor error correction to data outputted from the first interleaveprocessing means in a unit of data in the second direction, andoutputting the data to which the parity for error correction is added,second interleave processing means for executing a second interleaveprocess by writing data outputted from the parity adding means into asecond storage apparatus having a second matrix form in a fourthdirection of the second matrix coinciding with the second direction ofthe first matrix, and thereafter, reading from the second storageapparatus the data in a third direction perpendicular to the fourthdirection of the second matrix, and for outputting the data obtainedafter the second interleave process in a unit of data in the thirddirection, and transmitting means for transmitting data outputted fromthe second interleave processing means by way of a transmission line, asa transmission unit of a unit of data in the third direction.

Also, the above-mentioned packet transmission apparatus preferablyfurther comprises generating means, provided at a preceding stage of thefirst interleave processing means, for generating a transmission headerhaving a new identifier by deleting predetermined redundancy informationfrom the block information belonging to the plurality of blocks based onthe data string, and outputting data including a transmission unithaving the generated transmission header to the first interleaveprocessing means.

Further, in the above-mentioned packet transmission apparatus, thetransmitting means preferably transmits the transmission unit by an ATMtransmission system using the AAL TYPE 1 as an adaptation layer functionof an asynchronous transfer mode.

Furthermore, in the above-mentioned packet transmission apparatus, thetransmitting means preferably transmits the transmission unit by an ATMtransmission system using the AAL TYPE 5 as an adaptation layer functionof an asynchronous transfer mode.

According to the third aspect of the present invention, there isprovided a packet transmission apparatus comprising first parity addingmeans for adding a parity for error detection to a predetermined datastring in a direction in which the data string is aligned, andoutputting, in a predetermined unit of data, the data string to whichthe parity for error detection is added, first interleave processingmeans for executing a first interleave process by writing the datastring outputted from the first parity adding means into a first storageapparatus having a first matrix form in a first direction of the firstmatrix, and thereafter, reading from the first storage apparatus thedata in a second direction perpendicular to the first direction of thefirst matrix, and for outputting the data obtained after the firstinterleave process, in a unit of data in the second direction, secondparity adding means for adding a predetermined parity for errorcorrection to data outputted from the first interleave processing meansin a unit of data in the second direction, and outputting the data towhich the parity for error correction is added, second interleaveprocessing means for executing a second interleave process by writingdata outputted from the second parity adding means into a second storageapparatus having a second matrix form in a fourth direction of thesecond matrix coinciding with the second direction of the first matrix,and thereafter, reading from the second storage apparatus the data in athird direction perpendicular to the fourth direction of the secondmatrix, and for outputting the data obtained after the second interleaveprocess, in a unit of data in the third direction, and transmittingmeans for transmitting data outputted from the second interleaveprocessing means by way of a transmission line, as a transmission unitof a unit of data in the third direction.

Also, the above-mentioned packet transmission apparatus preferablyfurther comprises, generating means, provided at a preceding stage ofthe first parity adding means, for generating a transmission headerhaving a new identifier by deleting predetermined redundancy informationfrom the block information belonging to the plurality of blocks based onthe data string, and outputting data including a transmission unithaving the generated transmission header to the first parity addingmeans.

According to the fourth aspect of the present invention, there isprovided a packet transmission apparatus for transmitting in a packetform a transmission unit including a data string arranged so as todivide predetermined data into a plurality of blocks, wherein each blockhas a fixed length. The packet transmission apparatus according to thefourth aspect of the present invention comprises generating means forgenerating a plurality of transmission headers having a new identifierfrom block information belonging to a plurality of blocks based on thedata string, and outputting data including a transmission unit havingthe plurality of generated transmission headers, first interleaveprocessing means for executing a first interleave process by writingdata outputted from the generating means into a first storage apparatushaving a first matrix form in a first direction of the first matrix, andthereafter, reading from the first storage apparatus the data in asecond direction perpendicular to the first direction of the firstmatrix, and for outputting the data obtained after the first interleaveprocess in a unit of data in the second direction, parity adding meansfor adding a predetermined parity for error correction to data outputtedfrom the first interleave processing means in a unit of data in thesecond direction, and outputting the data to which said parity for errorcorrection is added, second interleave processing means for executing asecond interleave process by writing data outputted from the parityadding means into a second storage apparatus having a second matrix formin a fourth direction of the second matrix coinciding with the seconddirection of the first matrix, and thereafter, reading from the secondstorage apparatus the data in a third direction perpendicular to thefourth direction of the second matrix, and for outputting the dataobtained after the second interleave process in a unit of data in thethird direction, and transmitting means for transmitting data outputtedfrom the second interleave processing means by way of a transmissionline, as a transmission unit of a unit of data in the third direction,wherein the generating means arranges the plurality of transmissionheaders in the data including the transmission unit so that theplurality of transmission headers are positioned in different units ofdata in the third direction, respectively.

According to the fifth aspect of the present invention, there isprovided a packet transmission apparatus for transmitting in a packetform a transmission unit including a data string arranged so as todivide predetermined data into a plurality of blocks, wherein each blockhas a fixed length. The packet transmission apparatus according to thefifth aspect of the present invention comprises parity adding means foradding a predetermined parity for error correction to the data string ina predetermined unit of data, and outputting the data to which theparity for error correction is added, interleave processing means forexecuting an interleave process by writing data outputted from theparity adding means into a storage apparatus having a matrix form in afirst direction of the matrix, and thereafter, reading from the storageapparatus the data in a second direction perpendicular to the firstdirection of the matrix, and for outputting the data obtained after theinterleave process in a unit of data in the second direction, andtransmitting means for transmitting data outputted from the interleaveprocessing means by way of a transmission line, as a transmission unitof a unit of data in the second direction.

Also, in the above-mentioned packet transmission apparatus, the dataunit in the second direction is preferably a cell block unit of anasynchronous transfer mode.

Further, the above-mentioned packet transmission apparatus preferablyfurther comprises generating means, provided at a preceding stage of theparity adding means, for generating a transmission header having a newidentifier by deleting predetermined redundancy information from theblock information belonging to the plurality of blocks based on the datastring, and outputting data including a transmission unit having thegenerated transmission header to the parity adding means.

According to the sixth aspect of the present invention, there isprovided a packet transmission apparatus for transmitting in a packetform a transmission unit including a data string arranged so as todivide predetermined data into a plurality of blocks, wherein each blockhas a fixed length, and wherein block information for specifying a blocktype is added to each block. The packet transmission apparatus inaccordance with the sixth aspect of the present invention comprisesgenerating means for generating a transmission header having a newidentifier by deleting predetermined redundancy information from theblock information belonging to the plurality of blocks based on the datastring, and generating a transmission unit having the generatedtransmission header, packet forming means for dividing a data stringincluding the transmission unit generated by the generating means, intoa plurality of packets in a unit of MPG transport stream packets, andoutputting the plurality of packets, and transmitting means fortransmitting the plurality of packets outputted from the packet formingmeans by way of a transmission line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a construction of an ATM transmissionapparatus 1 according to a first preferred embodiment of the presentinvention;

FIG. 2 is a block diagram showing a construction of data outputted froman encoding unit 101 of FIG. 1;

FIG. 3 is a block diagram showing a construction of a video DIF block ofFIG. 2;

FIG. 4 is a block diagram showing a construction of a DIF dataprocessing circuit 104 of FIG. 1;

FIG. 5 is a block diagram showing a constructions of a header DIF blockand a subcode DIF block of FIG. 2;

FIG. 6 is a block diagram showing one of the VAUXDIF block, audio DIFblock and video DIF block of FIG. 2;

FIGS. 7(A)-7(D) are block diagrams showing an ID transform processexecuted by the DIF data processing circuit 104 of FIG. 4, wherein FIG.7(A) is a block diagram showing first 3-byte data before ID transform,FIG. 7(B) is a block diagram showing second 3-byte data before IDtransform, FIG. 7(C) is a block diagram showing third 3-byte data beforeID transform, and FIG. 7(D) is a block diagram showing 4-byte dataobtained after ID transform;

FIG. 8 is a block diagram showing a construction of a DIF dataprocessing circuit 104 a according to a second preferred embodiment ofthe present invention;

FIGS. 9(A) and 9(B) are block diagrams showing a packet block generatingmethod by means of a block buffer memory control circuit 6003 a of FIG.8, wherein FIG. 9(A) is a block diagram showing the whole body of thepacket block and FIG. 9(B) is a block diagram showing the contents of aheader 1703 of FIG. 9(A);

FIG. 10 is a block diagram showing a construction of a DIF dataprocessing circuit 104 b according to a third preferred embodiment ofthe present invention;

FIG. 11 is a block diagram showing a packet block generating method bymeans of a block buffer memory control circuit 6003 b of FIG. 10;

FIG. 12 is a block diagram showing a construction of an ATM transmissionapparatus 1 a according to a fourth preferred embodiment of the presentinvention;

FIG. 13 is a block diagram showing a construction of a DIF dataprocessing circuit 104 c of FIG. 12;

FIG. 14 is a block diagram showing a packet block generating method bymeans of a block buffer memory control circuit 6003 c of FIG. 13;

FIG. 15 is a block diagram showing a construction of a DIF dataprocessing circuit 104 d according to a fifth preferred embodiment ofthe present invention;

FIG. 16 is a block diagram showing a packet block generating methodexecuted by an ATM transmission apparatus provided with a DIF dataprocessing circuit 104 d of FIG. 15;

FIG. 17 is a memory map showing storage contents of an interleave buffermemory 1002 according to an interleave method executed by an interleavecontrol circuit 1003 of FIG. 15;

FIG. 18 is a block diagram showing a construction of a DIF dataprocessing circuit 1004 e according to a sixth preferred embodiment ofthe present invention;

FIG. 19 is a block diagram showing a packet block generating methodexecuted by an ATM transmission apparatus provided with a DIF dataprocessing circuit 104 e of FIG. 18;

FIG. 20 is a memory map showing storage contents of the interleavebuffer memory 1002 according to an interleave method executed by aninterleave control circuit 1003 a of FIG. 18;

FIGS. 21(A)-21(E) are views showing a construction of a seventhpreferred embodiment of the present invention, wherein FIG. 21(A) is ablock diagram showing a construction of a DIF data processing circuit104 f of the seventh preferred embodiment, FIG. 21(B) is a block diagramshowing data inputted from a block buffer memory 6002 to an interleavebuffer memory 3000 of FIG. 21(A), FIG. 21 (C) is a memory map showingstorage contents of an interleave buffer memory 3000 according to aninterleave method executed by an interleave control circuit 3001 of FIG.21(A), FIG. 21(D) is a block diagram showing data inputted from a parityadding circuit 3002 to an interleave buffer memory 3003 of FIG. 21(A),and FIG. 21(E) is a memory map showing storage contents of an interleavebuffer memory 3003 according to an interleave method executed by aninterleave control circuit 3004 of FIG. 21(A);

FIG. 22 is a block diagram showing an error distribution when cell lossoccurs in an ATM transmission apparatus provided with the DIF dataprocessing circuit 104 f of FIG. 21;

FIGS. 23(A) and 23(B) are views showing an interleave method of the DIFdata processing circuit 104 f of FIG. 21(A), wherein FIG. 23(A) is amemory map showing storage contents of the interleave buffer memory 3000according to the interleave method executed by the interleave controlcircuit 3001 of FIG. 21(A), and FIG. 23(B) is a memory map showingstorage contents of the interleave buffer memory 3003 according to theinterleave method executed by the interleave control circuit 3004 ofFIG. 21(A);

FIG. 24 is a memory map showing the detail of the storage contents ofthe interleave buffer memory 3003 according to the interleave methodexecuted by the interleave control circuit 3004 of FIG. 21(A);

FIG. 25 is a block diagram showing an error cell when cell loss occursin an ATM transmission apparatus provided with the DIF data processingcircuit 104 f of FIG. 21(A);

FIGS. 26(A)-26(E) are views showing a construction of an eighthpreferred embodiment of the present invention, wherein FIG. 26(A) is ablock diagram showing a construction of a DIF data processing circuit104 g of the eighth preferred embodiment, FIG. 26(B) is a block diagramshowing data inputted from the block buffer memory 6002 to the CRCadding circuit 3106 of FIG. 26(A), FIG. 26(C) is a block diagram showingdata inputted from a CRC adding circuit 3106 to an interleave buffermemory 3000 of FIG. 26(A), FIG. 26(D) is a memory map showing storagecontents of the interleave buffer memory 3000 according to theinterleave method executed by an interleave control circuit 3001 of FIG.26(A), FIG. 26(E) is a block diagram showing data inputted from a parityadding circuit 3002 to the interleave buffer memory 3003 of FIG. 26(A),and FIG. 26(F) is a memory map showing storage contents of theinterleave buffer memory 3003 according to the interleave methodexecuted by an interleave control circuit 3004 of FIG. 26(A);

FIG. 27 is a memory map showing storage contents of the interleavebuffer memory 3003 according to the interleave method executed by theDIF data processing circuit 104 g of FIG. 26(A);

FIG. 28 is a block diagram showing a packet block generating methodexecuted by an ATM transmission apparatus provided with the DIF dataprocessing circuit 104 g of FIG. 26(A);

FIG. 29 is a view showing a construction of a

FIGS. 29(A)-29(E) are views showing a construction of a ninth preferredembodiment of the present invention, wherein FIG. 29(A) is a blockdiagram showing a construction of a DIF data processing circuit 104 h ofthe ninth preferred embodiment, FIG. 29(B) is a block diagram showingdata inputted from the block buffer memory 6002 to the interleave buffermemory 3000 of FIG. 29(A), FIG. 29(C) is a memory map showing storagecontents of the interleave buffer memory 3000 according to an interleavemethod executed by the interleave control circuit 3001 of FIG. 29(A),FIG. 29(D) is a block diagram showing data inputted from the parityadding circuit 3002 to the interleave buffer memory 3003 of FIG. 29(A),and FIG. 29(E) is a memory map showing storage contents of theinterleave buffer memory 3003 according to an interleave method executedby an interleave control circuit 3004 of FIG. 29(A);

FIG. 30 is a memory map that shows a packet block generating methodexecuted by the DIF data processing circuit 104 h of FIG. 29(A), andthat shows the detail of the storage contents stored in an interleavebuffer memory 3003 of FIG. 29(A);

FIG. 31 is a block diagram showing a construction of an ATM transmissionapparatus 1 b according to a tenth preferred embodiment of the presentinvention;

FIG. 32 is a block diagram showing an ATM cell formation processexecuted by the ATM cell forming circuit 105 a of FIG. 31;

FIG. 33 is a block diagram showing a construction of a DIF processingcircuit 104 i according to an eleventh preferred embodiment of thepresent invention;

FIG. 34 is a block diagram showing a packet block generating methodexecuted by an ATM transmission apparatus provided with the DIF dataprocessing circuit 104 i of FIG. 33;

FIG. 35 is a memory map showing storage contents of an ATM cell blocksequence buffer memory 1402 according to a packet block generatingmethod executed by the interleave control circuit 1403 of FIG. 33;

FIGS. 36(A)-36(E) are views showing a construction of a twelfthpreferred embodiment of the present invention, wherein FIG. 36(A) is ablock diagram showing a construction of the DIF data processing circuit104 j of the twelfth preferred embodiment, FIG. 36(B) is a block diagramshowing data inputted from a block buffer memory 6002 to the interleavebuffer memory 2600 of FIG. 36(A), FIG. 36(C) is a memory map showingstorage contents of the interleave buffer memory 2600 according to aninterleave method executed by an interleave control circuit 2601 of FIG.36(A), FIG. 36(D) is a block diagram showing data inputted from a parityadding circuit 2602 to an interleave buffer memory 2603 of FIG. 36(A),and FIG. 36(E) is a memory map showing storage contents of an interleavebuffer memory 2603 according to an interleave method executed by aninterleave control circuit 2604 of FIG. 36(A);

FIG. 37 is a block diagram showing a packet block generating method ofan ATM transmission apparatus provided with a DIF data processingcircuit 104 j of FIG. 36(A);

FIG. 38 is a block diagram showing a structure of data outputted fromthe ATM cell forming circuit 105 of the ATM transmission apparatusprovided with the DIF data processing circuit 104 j of FIG. 36(A);

FIG. 39 is a block diagram showing a construction of an ATM transmissionapparatus 1 c according to a thirteenth preferred embodiment of thepresent invention; and

FIG. 40 is a block diagram showing a packet block generating methodexecuted by the ATM transmission apparatus 1 c of FIG. 39.

BEST MODE FOR CARRYING OUT THE INVENTION PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described indetail below with reference to the accompanying drawings.

In regard to the preferred embodiments of the present invention, therewill be described an example in which compressed image data, audio dataand additional information are transmitted in accordance with thestandard of the household digital VTR in an ATM network to be used as acommunications network. Herein is used the “DVC Standard” according tothe agreement made by the HD DIGITAL VCR CONFERENCE as the standard ofthe household digital VTR.

The ATM standard is standardized by and disclosed in ITU-TRecommendation Q. 2931, ITU-T Recommendation I. 363, The ATM Forum, ATMUser-Network Interface Specification Version 3.0 (referred to as UNI3.0hereinafter), The ATM Forum, ATM User-Network Interface SpecificationVersion 3.1 (referred to as UNI3.1 hereinafter), The ATM Forum, ATMUser-Network Interface Specification Version 4.0 (referred to as UNI4.0hereinafter) and so on.

The DVC Standard is mentioned in “Specifications of Household DigitalVCRs using 6.3 mm magnetic tape” December, 1994 HD DIGITAL VCRCONFERENCE (referred to as a first reference hereinafter), and thedigital interface thereof is mentioned in “Specifications of DigitalInterface for Consumer Electric Audio/Video Equipment” December, 1995 HDDIGITAL VCR CONFERENCE (referred to as a second reference hereinafter).

It is to be noted that the preferred embodiments of the presentinvention can be applied to not only the above-mentioned DVC Standardbut also the DVCPRO Standard that is the standard for broadcastingstations using an identical image compression system.

The DVCPRO Standard is mentioned in “Proposed SMPTE Standard for DigitalVideo Recording with video compression at 25 Mb/s 6.35 mm Type D-7Component Format 525/60 and 625/50(DVCPRO): Final version Dec., 241997”.

In the following description, there is no hindrance if the DVC, DVCStandard and DVC data are replaced by DVCPRO, and this does notinfluence the subject matter of the present invention.

First Preferred Embodiment

FIG. 1 is a block diagram showing a construction of an ATM transmissionapparatus 1 according to a first preferred embodiment of the presentinvention. In FIG. 1 and the other figures, the triangular mark locatedin the upper right-hand position of each block indicates that the blockis the characteristic portion of the preferred embodiment. In FIG. 1 areshown an encoding unit 101, an ATM transmission terminal unit 102, aninput terminal 103 of the ATM transmission terminal unit 102, a digitalinterface data processing circuit 104 (referred to as a DIF dataprocessing circuit hereinafter, and the digital interface will bereferred to as DIF hereinafter), an ATM cell forming circuit 105, anetwork interface 106 and an output terminal 107 for an ATM network 100.In this case, the ATM transmission apparatus 1 is constituted bycomprising the DIF data processing circuit 104 and the ATM transmissionterminal unit 102, wherein the ATM transmission terminal unit 102 isconstituted by comprising the ATM cell forming circuit 105 and thenetwork interface 106.

In the construction shown in FIG. 1, a data string including encodedcompressed image and audio data as well as additional information isoutputted from the encoding unit 101, and then, is inputted via theinput terminal 103 to the DIF data processing circuit 104 of the ATMtransmission apparatus 1. The DIF data processing circuit 104 generatesa transmission header having a new identifier by deleting predeterminedredundancy information from block information belonging to a pluralityof blocks based on the inputted data string, generates a transmissionunit having the generated transmission header, and then, outputs thetransmission unit to the ATM cell forming circuit 105 as described indetail later. In response to this, the ATM cell forming circuit 105generates a packet to be transmitted by dividing the inputted dataincluding the transmission unit into ATM cell blocks, and then, outputsthe packet to the network interface 106. In response to this, thenetwork interface 106, which is provided with a transmitter and areceiver for the ATM network 100, transmits the inputted packet via theoutput terminal 107 to the ATM network 100, thereby transmitting thepacket to the ATM transmission terminal unit of the destinationindicated by the transmission header.

FIG. 2 is a block diagram showing a construction of data outputted fromthe encoding unit 101 of FIG. 1, and the form of the data is mentionedin the above-mentioned second reference. The data stream shown in FIG. 2is constructed of a series of a plurality of blocks, each block beingcalled the DIF block. Data of one frame is constructed by repeating theseries of data sequence shown in FIG. 2, and therefore, the data streamof FIG. 2 is called the subsequence in the following description.

In FIG. 2, HO denotes a header DIF block, SC0 and SC1 denote subcode DIFblocks, VA0, VA1 and VA2 denote video AUX DIF blocks (referred to asVAUX hereinafter) and A0, A1, . . . , A8 denote audio DIF blocksinserted between video DIF blocks described later. Further, V0, V1, . .. , V134 denote the video DIF blocks. Each DIF block is constructed of atotal of 80 bytes comprised of a 3-byte ID and 77-byte data as shown inFIG. 3.

The header DIF block is mounted with control information relevant to thesubsequence, the audio DIF block is mounted with audio data andauxiliary data relevant to audio, the video DIF block is mounted withvideo data, the video AUXDIF block is mounted with auxiliary datarelevant to video and the subcode block is mounted with other additionalinformation.

FIG. 3 is a block diagram showing a construction of the video DIF blockof FIG. 2. In FIG. 3, the data of the video DIF block is constructed bydividing the screen into small units, each unit being called the macroblock and subjecting the blocks to DCT transform or the like.

Among the 80 bytes of the video DIF block, the first three bytesrepresent an ID, and the higher-order four bits of the next one byterepresent the error status (SAT). The error status stores informationindicating whether an error exists in the DIF block, indicating whetherthe DIF block is the error-corrected or error-concealed DIF block, andindicating what correction method is used in the case of theerror-corrected or error-concealed DIF block. The lower-order four bitsrepresent the quantization number (QNO), and the succeeding blocks eachhaving 14 bytes represent the luminance signal information (Y0, Y1, Y2and Y3) of each macro block, and the succeeding two blocks each having10 bytes represent the color-difference signal information (CR, CB), morepresents the DCT mode, and C0 and C1 represent the class number. It isto be noted that FIG. 3 is identical to the above-mentioned DVCPROstandard of “Proposed SMPTE Standard for Digital Video Recording withvideo compression at 25 Mb/s 6.35 mm Type D-7 Component Format 525/60and 625/50 (DVCPRO): Final version Dec. 24, 1997” of FIG. 40, and thecompression method is also described in detail in the same reference.

What is important in the preferred embodiment of the present inventionis the fact that the information representing the error status of eachvideo DIF block is only one.

As shown in FIG. 2, there is a total of 150 DIF blocks comprised of oneheader DIF block, two subcode DIF blocks, three VAUXDIF blocks, nineaudio DIF blocks and 135 video DIF blocks, and then, the 150 DIF blocksform one. subsequence having a total of 80 bytes×150=12000 bytes.

According to the NTSC system having 525 scanning lines and 60 frames(referred to as a 525/60 system hereinafter), 10 subsequences constituteone frame data.

According to the PAL system having 625 scanning lines and 50 frames(referred to as a 625/50 system hereinafter), 12 subsequences constituteone frame data. Therefore, the number of DIF blocks in one frame becomes150×10=1500 in the 525/60 system or becomes 150×12=1800 in the 625/25system. The following description is based on an example of the 525/60system.

The first-preferred embodiment is characterized in that the DIF blocksare subjected to transform for data amount reduction. Specifically, whencollectively handling a plurality of DIF blocks as one transmissionunit, the 3-byte ID inside each DIF block is not always necessary forevery DIF block, and the data amount reduction is executed by making oneID represent all the IDs or replacing the IDs with another ID having asmaller data amount than the data amount of all the IDs. Furthermore,the data amount reduction is executed by reducing the redundant datasuch as the reserved data and/or invalid data in the data.

FIG. 5 is a block diagram showing a constructions of the header DIFblock and the subcode DIF block of FIG. 2, where is shown a blocktransform of the header and subcode blocks constituting the three DIFblocks located at the head of the subsequence.

In FIG. 5 are shown a header DIF block (H0) 3001, a subcode DIF block(SC0) 3002, and a subcode DIF block (SC1) 3003. In the present preferredembodiment, reduction of the data amount is executed with the abovethree DIF blocks (240 bytes in total) used as a transmission unit of 141bytes (denoted by 3004). The sections of 72 bytes, 29 bytes and 29 bytesat the tail of the three DIF blocks 3001, 3002 and 3003 are reserveddata.

First of all, the ID of three bytes in each of the above three DIFblocks (nine bytes in total) is reduced to four bytes by a method asdescribed later with reference to FIG. 7 for the execution of dataamount reduction. Next, since the valid data of the header DIF block H0has five bytes, the 5-byte valid data is continuously placed closely.Next, each of the valid data of the subcode DIF block SC0 and the validdata of the subcode DIF block SC1 has 48 bytes, the data aresuccessively placed closely. Finally, 36-byte dummy data is insertedinto the hindmost portion of the transmission unit 3004 as shown in thehatched section. It is to be noted that additional information may beinserted in this hatched section.

The transmission unit 3004 has a total of 141 bytes, and therefore, thetransmission unit 3004 can be divided into three blocks each having 47bytes as denoted by 3005.

FIG. 6 is a block diagram showing a block transform process of one ofthe VAUXDIF block, audio DIF block and video DIF block of FIG. 2. InFIG. 6, the reference numeral 4001 denotes continuous three blocks ofthe above DIF blocks in the subsequence. There are continuous threeblocks of, for example, “VA0, VA1, VA2”, “A0, V0, V1” and “V2, V3, V4”.

First of all, the 3-byte IDs of the continuous three blocks are reducedto four bytes by the method described later (See FIG. 7) for theexecution of data amount reduction. Next, 77 bytes of the data sectionof each DIF block are successively placed closely. As a result, the dataof 240 bytes of the original data block 4001 can be reduced to 235 bytesas denoted by a transmission unit 4002, thereby allowing the data amountreduction to be achieved. The transmission unit 4002 can be divided intofive blocks each having 47 bytes as denoted by 4003.

FIG. 7 is a block diagram showing an ID transform process executed bythe DIF data processing circuit 104 of FIG. 4, wherein FIG. 7(A) is ablock diagram showing first 3-byte data before ID transform, FIG. 7(B)is a block diagram showing second 3-byte data before ID transform, FIG.7(C) is a block diagram showing third 3-byte data before ID transformand FIG. 7(D) is a block diagram showing 4-byte data obtained after IDtransform.

As described with reference to FIG. 5 and FIG. 6, in the first preferredembodiment, the data amount reduction is executed by transforming theIDs each having three bytes of the three DIF blocks into one ID of fourbytes.

In FIG. 7, SCT denotes the section type, Seq denotes the sequencenumber, Dseq denotes the DIF sequence number and DBN denotes the DIFblock number. A bit number is attached to the tail of each code, and thebit number is followed by a hyphen (-) and the serial number “0” in FIG.7(A), the serial number “1” in FIG. 7(B) and the serial number “2” inFIG. 7(C). It is to be noted that RSV denotes reserved data.

The section type SCT indicates the type of the DIF block, where thetypes of the header, subcode, VAUX, audio and video are expressed bythree bits. The sequence number Seq indicates the correspondence to acolor frame type. The DIF sequence number Dseq indicates the subsequencenumber. Since the 525/60 system is comprised of 10 subsequences, thevalues of 0 to 9 are expressed by four bits. Since the 625/50 system iscomprised of 12 subsequences, the values of 0 to 11 are expressed byfour bits.

The DIF block number DBN indicates the number of the DIF block in thesubsequence by eight bits. For example, 135 video DIF blocks exist inone subsequence, and therefore, the values of 0 to 134 are expressed bybinary digits. Nine audio DIF blocks exist in one subsequence, andtherefore, the values of 0 to 8 are expressed by binary digits.

This first preferred embodiment directs its attention to the fact thatthree pieces of common data are not necessary for the IDs whenintegrating three IDs into one ID and only one DIF block number isnecessary when integrating the IDs of continuous DIF blocks by aprescribed method. Specifically, the sequence numbers Seq are identicalwithin the subsequence among the bits constituting the IDs, and there isno need for transmitting all the three blocks. The DIF sequence numbersDseq are identical or the same within the subsequence, and there is noneed for transmitting all the three blocks. The DIF block numbers DBN ofall the three blocks are not necessary if the inputted data string issubjected to the block transform in the prescribed order.

As described above, as shown in FIG. 7(D), a new ID is constructed bybringing the arrangement of FIG. 7(A) as it is into the places of thefirst three bytes and bringing into the place of the fourth byte thehigher-order three bits of the section type SCT of (B), the reserve bit,the three bits of the section type SCT of (c) and the reserve bit inthis order. With this arrangement, the amount of data comes to have adata length of 235 bytes (p=235<3×80) by reducing the redundancyinformation from the three (m=3) blocks, each block having a fixedlength of 80 bytes (n=80).

According to the method shown in FIG. 5 to FIG. 7, there are threeblocks of 47 bytes of the header DIF block and the subcode DIF block.Since the VAUX, the audio DIF block and the video DIF block arecomprised of a total of 147 DIF blocks, there are (147/3)×5=245 47-byteblocks. Accordingly, there is a total of 248 47-byte blocks of all theDIF blocks. The data amount of 47 bytes, which corresponds to thepayload of the AAL TYPE 1 of the ATM, will be referred to as an ATM cellblock in the following description.

It is to be noted that the three IDs (DIF blocks) are integrated intoone in the first preferred embodiment, the present invention is notlimited to this, and it is acceptable to integrate another number ofIDs.

Although the method shown in FIG. 7 has been described by taking thecontinuous three DIF blocks as an example, the continuation is not theessential factor, and the case where the ID information is reduced froma plurality of arbitrary DIF blocks is not excluded from the scope ofthe present invention.

When integrating continuous three DIF blocks into one, it is sometimesthe case where the audio DIF block and the video DIF block are mixedwith each other. Therefore, newly-constructed three IDs (See FIG. 7(D))are inserted only for the section type SCT. With this arrangement, evenwhen the audio DIF block and the video DIF block are mixed with eachother, their positions in the subsequence can be identified by the threesection types of the newly-constructed three IDs (See FIG. 7(D)) and theblock numbers.

FIG. 4 is a block diagram showing a construction of the DIF dataprocessing circuit 104 of FIG. 1 for executing block transform. In FIG.4 is shown an input terminal 6001 to which the DIF block subsequence isinputted. There are shown a block buffer memory 6002, a block buffermemory control circuit 6003 and an output terminal 6004.

The block buffer memory 6002 can store therein continuous three DIFblocks. The data write and read control of the block buffer memory 6002is executed by the block buffer memory control circuit 6003.

In regard to the DIF subsequence inputted from the input terminal 6001,three DIF blocks are written into the block buffer memory 6002 under thecontrol of the block buffer memory control circuit 6003. The reading isexecuted by designating the address of the block buffer memory 6002according to the method shown in FIG. 5 for the header DIF block and thesubcode DIF block and according to the method shown in FIG. 6 for theVAUXDIF block, the audio DIF block and the video DIF block. The blockbuffer memory 6002 is constructed of two buffer memories, where writingand reading are alternately executed.

The block buffer memory control circuit 6003 is provided with a DIFblock counter for counting DIF blocks, and the counter is counting theDIF blocks that are being currently written and the DIF blocks that arecurrently being read. The read address is preliminarily fixed accordingto the methods shown in FIG. 5 and FIG. 6, and therefore, the readaddress can be simply generated by storing a control program of themethods into a ROM of a small storage capacity and incorporating the ROMinto the block buffer memory control circuit 6003.

According to the ID transform shown in FIG. 7, there is required acircuit for forming eight bits by adding the higher-order four bits ofthe first byte of FIG. 7(B) and the higher-order four bits of the firstbyte of FIG. 7(C) to the fourth byte of FIG. 7(D). This circuit can beconstructed by, for example, a simple register and incorporated into theblock buffer memory 6002.

The output terminal 6004 of the DIF data processing circuit 104 of FIG.4, first of all, outputs three ATM cell blocks from the header DIF blockand the subcode DIF blocks from the head of the DIF block subsequence asindicated by 3005 in FIG. 5. Subsequently, as indicated by 4003 in FIG.6, 245 ATM cell blocks are outputted from the VAUX, the audio DIF blockand the video DIF block.

As described above, according to the first preferred embodiment, theamount of ID information can be further reduced by integrating three DIFblocks, producing the effects as follows.

Only a total of 248 ATM cell blocks constructed of 47 bytes areoutputted, and therefore, the total data amount becomes 11656 bytes. Theoriginal DIF block subsequence has 150 DIF blocks of 80 bytes, andaccordingly, the data has 12000 bytes. Therefore, a data amountreduction of:

(12000−11656)/12000×100=2.87%

can be achieved. In terms of the ATM cell block, this leads to require256 ATM cells for transmitting the original data since:

12000/47=255.3,

however, the original data can be transmitted by 248 ATM cells in thefirst preferred embodiment as described above.

According to the first preferred embodiment of the present invention,the communications load can be remarkably reduced and the use of theresources of the communications network can be reduced. By virtue of thereduction in amount of communications, the communications time becomesshort, thereby improving the reliability of the real-time communicationsby that much or degree. The communications zone used by the ATM networkis reduced, the load applied on the network becomes small and the loadapplied on an ATM switching process becomes small. Therefore, theprobability of the cell disposal or the like becomes small, so thathighly-reliable communications tolerant of cell loss can be achieved.Furthermore, this preferred embodiment can be achieved with a verysimple circuit construction.

The data sequence obtained after the DIF block subsequence process asdescribed in the first preferred embodiment will be referred to as anATM cell block sequence. The ATM cell block sequence is constructed of11656 bytes as described above.

The system of the first preferred embodiment is used in the followingpreferred embodiments, and the numbers of the circuit block diagramshown in FIG. 4 are also used for the same blocks in the other figures.

The system of the first preferred embodiment is also used as dataprocessing means for executing the process appropriate for subordinatelayers in the preferred embodiments described as follows.

Although the ATM is used as the transmitting means for the explanationof the first preferred embodiment, the transmitting means is not limitedto the ATM. The subject matter of the present invention capable ofreducing the amount of communications does not change even when anEthernet or a fiber channel is used, and no transmitting means isexcluded from the scope of the invention of the present application.

Second Preferred Embodiment

FIG. 8 is a block diagram showing a construction of a DIF dataprocessing circuit 104 a according to a second preferred embodiment ofthe present invention. This second preferred embodiment is characterizedin that the data amount reduction is executed by executing DIF blocktransform. In the second preferred embodiment, the 3-byte ID in each DIFblock is not always necessary for all the DIF blocks when collectivelyhandling a plurality of DIF blocks as one transmission unit similar tothat of the first preferred embodiment, and the data amount reduction isexecuted by replacing the IDs with another ID having a smaller dataamount than the data amount of all the IDs.

FIGS. 9(A) and 9(B) are block diagrams showing a packet block generatingmethod by means of the block buffer memory control circuit 6003 a ofFIG. 8, wherein FIG. 9(A) is a block diagram showing the whole body ofthe packet block and FIG. 9(B) is a block diagram showing the contentsof the header 1703 of FIG. 9(A). FIG. 9(A) shows the DIF blocktransform, by which six DIF blocks are integrated into one block. Thereference numeral 1700 denotes six DIF blocks. The six DIF blocks may besix DIF blocks of a continuous subsequence or arbitrary six DIF blocksaccording to a prescribed method. The DIF blocks are not limited tothose inside the subsequence, and the DIF blocks may be those acrosssubsequences.

The reference numeral 1701 denotes a data block obtained by collectingonly the valid data of each DIF block. Each DIF block has valid data of77 bytes, and therefore, this results in 6×77=462 bytes. Then, asdenoted by the reference numeral 1702, a header 1703 is attached to thehead of the data block 1701. The reference numeral 1702 will refer to atransmission unit hereinafter.

FIG. 9(B) shows the detail of the header 1703. In the second preferredembodiment, the header 1703 is constructed of five bytes, among whichthe first four bytes represent a time code (TC) and the last one byterepresents the sequence number (SNo) inside one frame.

In regard to the time code, for example, the subcode block of the DIFblock has time code information of four bytes, and therefore, it isproper to use the data as it is. The time code is not limited to theinformation inside the subcode, and an independent time code may beattached. The time code is not limited to four bytes.

The time code is, for example, HH-hour MM-minute SS-second FF-frame(referred to as an HH:MM:SS:FF frame hereinafter). For example, if then-th frame is 01:02:03:00, then the time code increases every frame asexemplified by 01:02:03:01 for the (n+1)-th frame and 01:02:03:02 forthe (n+2)-th frame. By this time code, the video frame to which eachtransmission unit belongs can be identified.

The subsequence shown in FIG. 2 is constructed of 150 DIF blocks, andone frame is constructed of 10 subsequences. Accordingly, there is atotal of 1500 DIF blocks. Each transmission unit is constructed of sixDIF blocks, and therefore, one frame data is constructed of 1500/6 250transmission units. By attaching the numbers of 0 to 249 to the sequencenumber (SNo) inside one frame of FIG. 9(B), the transmission unit insideone frame can be identified.

For example, the foremost transmission unit of the foremost subsequenceof the first frame is constructed of six DIF blocks of H0, SC0, SC1,VA0, VA1, and VA2 of FIG. 2, and the sequence number SN is zero. Thenext transmission unit is constructed of six DIF blocks of A1, V0, V1,V2, V3, V4 and V5, and the sequence number SN is one. One subsequence isconstructed of:

150/6=25

transmission units, and therefore, the foremost transmission unit of thenext subsequence is constructed of six DIF blocks of H0, SC0, SC1, VA0,VA1 and VA2 of FIG. 2, and the sequence number (SNo) is twenty five.

As described above, in the present preferred embodiment, the sequencenumbers (SNo) are sequentially attached to the transmission units insideone frame.

As a transmitting means, there can be used the ATM, Ethernet, fiberchannel or the like as exemplified in the first preferred embodiment forthe achievement of transmission.

As described above, according to the present preferred embodiment, thesix 80-byte DIF blocks are integrated into the 467-byte transmissionunit 1702 with the header, and therefore, an information amountreduction of:

(80×6−467)/(80×6)×100 2.7%

can be achieved, so that an advantageous effect similar to that of thefirst preferred embodiment can be obtained.

Although a circuit similar to the DIF data processing circuit 104 of thefirst preferred embodiment of FIG. 4 is used for materializing thesecond preferred embodiment, a block buffer memory control circuit 6003a having a varied packet block generating method as shown in FIG. 8 isemployed. The method shown in FIG. 9 is fixed, and therefore, the readaddress can be easily generated by executing the writing into the blockbuffer memory 6002 in the order of the data inputted from the inputterminal 6001, storing a read control program into a ROM of a smallstorage capacity and integrating the ROM into the block buffer memorycontrol circuit 6003.

In regard to the time code of the header 1703 of the transmission unit1702, when using the one stored in the subcode, it is proper to providethe block buffer memory 6002 with a buffer memory specially for the timecode (TC), store the time code (TC) in accordance with the timing atwhich the time code (TC) is inputted, and output the time code inaccordance with the timing of the head of each transmission unit 1702.The time required for the detection of the time code (TC) inside thesubcode can be easily adjusted by delaying the read timing from theblock buffer memory 6002.

When an individual time code (TC) is independently attached, a simplecounter to be incremented every frame is used. It is proper to reset thesequence number SNo at the head of the frame and increment the sequencenumber for each transmission unit.

Although the transmission unit of the second preferred embodiment isgenerated from the six DIF blocks, the present invention is not limitedto this number, and it is a matter of course that the reduction amountof the DIF block headers is greater when the transmission unit isgenerated from a greater number of DIF blocks, for the achievement of ahigh reduction rate of the total amount of information.

Third Preferred Embodiment

FIG. 10 is a block diagram showing a construction of a DIF dataprocessing circuit 104 b according to a third preferred embodiment ofthe present invention. This third preferred embodiment is characterizedin that a transmission unit is generated from a greater number of DIFblocks than those of the second preferred embodiment in the firstpreferred embodiment.

FIG. 11 is a block diagram showing a packet block generating method bythe block buffer memory control circuit 6003 b of FIG. 10. FIG. 11 showsa DIF block transforming process, which forms a transmission unit 1804from 75 DIF blocks 1800. The reference numeral 1801 denotes a data blockobtained by collecting only the valid data of each DIF block. If thedata blocks are collected, then this results in a total of 77 (75=5775bytes as denoted by 1801. A transmission unit header 1803 indicated bythe hatching in a data block 1802 has five bytes identical to thatdescribed with reference to FIG. 9(B) in the second preferredembodiment. Therefore, the data block 1802 has 5780 bytes. In this case,each data block 1802 is constructed of 75 DIF blocks, and therefore, thedata of one frame is constructed of 1500/6=20 transmission units.Therefore, by giving serial numbers of 0 to 19 to the sequence numbersSNo in one frame, the transmission unit in one frame can be identified.

As a transmitting means, there can be used the ATM, Ethernet, fiberchannel or the like as exemplified in the first preferred embodiment forthe achievement of transmission.

As described above, the 75 DIF blocks of 80 bytes are integrated intothe transmission unit 1802 of 5780 bytes in the third preferredembodiment, and therefore, an information amount reduction of:

(80×75−5780)/(80×75)×100=3.6%

can be achieved, so that an advantageous effect similar to that of thefirst preferred embodiment can be obtained.

Although a circuit similar to the DIF data processing circuit 104 of thefirst preferred embodiment of FIG. 4 is used for materializing the thirdpreferred embodiment, the block buffer memory control circuit 6003 bhaving a varied packet block generating method as shown in FIG. 10 isemployed.

The dummy data is added next to the header 1803 of the transmission unit1804, and the adding of the dummy data can be achieved by outputting apredetermined value in accordance with a predetermined timing from theblock buffer memory 6002. For example, it is acceptable to preparatorilystore dummy data in the block buffer memory 6002, and then, output thedata.

The dummy data adding timing is controlled by the block buffer memorycontrol circuit 6003 b and is able to be easily realized by deciding thedummy data adding timing by means of a counter or the like andindicating the address in which the dummy data is stored inside theblock buffer memory 6002.

Fourth Preferred Embodiment

FIG. 12 is a block diagram showing a construction of an ATM transmissionapparatus 1 a according to a fourth preferred embodiment of the presentinvention. FIG. 13 is a block diagram showing a construction of a DIFdata processing circuit 104 c of FIG. 12. The fourth preferredembodiment is characterized in that the ATM cell block sequence of thefirst preferred embodiment is used as an example of data to betransmitted and the ATM transmission terminal unit 102 transmits a datapacket by means of an adaptation layer protocol prescribed by the AALTYPE 1 of the ATM.

FIG. 14 is a block diagram showing a packet block generating method bythe block buffer memory control circuit 6003 c of FIG. 13. In the fourthpreferred embodiment, as described above, the transmission of datapacket is executed by means of the protocol of the AAL TYPE 1 of theATM. A protocol stack is shown on the left-hand side of FIG. 14.

In FIG. 14, the reference numeral 7001 denotes an TM cell block sequence(3005 of FIG. 5 and 4003 of FIG. 6) as described in the first preferredembodiment. The reference numeral 7002 denotes a user information regionof CS (Convergence Sublayer) of an AAL layer. The reference numeral 7003denotes the data construction of a SAR (Segmentation and Re-assembly)sublayer of the AAL layer. The reference numeral 7004 denotes the cellof the AAL layer. These abbreviations are also used in the followingdescription.

The ATM cell block sequence 7001 is constructed of 248 ATM cell blocksof 47 bytes as described in the first preferred embodiment. In the CS,the ATM cell blocks are conceptually integrated into one as userinformation and transmitted to the SAR layer. In the SAR layer, a 4-bitsequence number (SN) and a 1-byte CRC (SNP) or the like for protectingthe 4-bit sequence number are added to every 47 bytes of the SAR layeraccording to the AAL TYPE 1 protocol, and the resulting 48 bytes aretransmitted to the ATM layer.

In this case, CRC is a cyclic redundancy check parity for detecting anerror. In the ATM layer, as indicated by the hatched section of the ATMcell 7004, a 5-byte ATM cell header is added for the formation an ATMcell.

As described in the first preferred embodiment, the ATM cell blocksequence 7001 is divided in a unit of 47 bytes, and therefore, each ATMcell block equivalently corresponds to the ATM cell 7004 of the ATMlayer on a one-to-one basis, meaning that no useless data is added.Therefore, the layer of AAL TYPE 1 can be easily utilized without anyadditional circuit. It is to be noted that the CS data 7002 of the AALexists only conceptually, and actually each ATM cell block 7001 has 47bytes. Therefore, each ATM cell block can also be directly mapped to thelayer of the SAR data 7003 of the AAL.

As a circuit for materializing this fourth preferred embodiment, a blockbuffer memory control circuit 6003 c that is similar to the DIF dataprocessing circuit 104 of the first preferred embodiment of FIG. 4 andhas a varied packet block generating method as shown in FIG. 13 isemployed.

In FIG. 12, the ATM cell forming circuit 105 constitutes the ATM cell7004 by collecting the ATM cell blocks 7001 and adding necessary data tothe blocks as shown in FIG. 14, and then, outputs the ATM cell. In thiscase, the ATM cell forming circuit 105 executes the processing of theAAL layer and the ATM layer as described above. As circuits for theseprocesses, equipments for executing transmission by the AAL TYPE 1protocol are currently popularized, and the circuits can be easilyrealized by using them. In regard to the network interface 106, thereare popularized ATM physical layer LSI and so on, and the networkinterface can be easily achieved by using them. Therefore, the AALlayer, the ATM layer and the ATM physical layer can be easily realizedat low cost.

As described above, in the fourth preferred embodiment, a data amountreduction of 2.87% can be achieved similar to that of the firstpreferred embodiment, so that the communications load can be remarkablyreduced and the use of the resources of the communications network canbe reduced. By virtue of the reduction in the amount of communications,the communications time becomes short and the reliability of thereal-time communications is improved by that much or degree.Furthermore, by reducing the amount of communications, a load applied onan ATM switch and so on inside the network is also reduced and theprobability of the cell loss or the like is also reduced, so thathigh-quality transmission can be achieved. Furthermore, the currentlypopularized equipments such as the equipments for the AAL TYPE 1 use orthe like can be used as they are and the construction of the circuit tobe added can be realized very simply, so that the preferred embodimentcan be achieved very easily at low cost.

In particular, when the data reduction method as described in the firstpreferred embodiment is used, the data amount is exactly adjusted to thepayload of the AAL TYPE 1. Therefore, the data transmission can beefficiently executed and the adding of a processing circuit for puttingthe data on the AAL TYPE 1 is made very simple, so that the circuitscale can be remarkably reduced.

Furthermore, the DIF block subsequence and the ATM cell block sequencehave a constant amount of information. Therefore, by using the AAL TYPE1 of the ATM transmission protocol appropriate for the transmission ofsound and image at a fixed rate, the reliability of the real-timecommunications is improved. Even when the ATM cell loss occurs due tothe logical coincidence of the direction in which the ATM cell istransmitted with the direction of the DIF block, the DIF block error islimited to a minimum of one or two in number, so that a transmissionsystem which causes a very small amount of disorder of image and soundeven when the ATM cell loss occurs can be provided.

Although the fourth preferred embodiment has been described based on theATM cell block sequence as described in the first preferred embodiment,the subject matter of the present invention is to efficiently executethe transmission by the AAL TYPE 1 protocol by reducing the data amount.A similar effect can be obtained even when the data amount reductionmethod of the second preferred embodiment or the third preferredembodiment or another data amount reduction method is used, and suchmethods are not excluded from the scope of the present invention.

Fifth Preferred Embodiment

FIG. 15 is a block diagram showing a construction of a DIF dataprocessing circuit 104 d according to a fifth preferred embodiment ofthe present invention. This fifth preferred embodiment is characterizedin that the transmission is executed by means of the AAL TYPE 1 of theATM after subjecting the ATM cell block sequence to an interleaveprocess and a process for error correcting. As shown in FIG. 15, thepreferred embodiment is characterized in that a parity adding circuit1001, an interleave buffer memory 1002 and an interleave control circuit1003 are further provided as compared with the DIF data processingcircuit 104 of the first preferred embodiment of FIG. 4.

That is, the DIF data processing circuit 104 d of the fifth preferredembodiment is characterized in that the circuit adds a parity for FEC tothe generated transmission unit, thereafter subjects the data includingthe added Parity for FEC to the interleave process, and then, outputsthe data obtained after the interleave process as a transmission unit.

FIG. 16 is a block diagram showing a packet block generating methodexecuted by an ATM transmission apparatus provided with the DIF dataprocessing circuit 104 d of FIG. 15. In FIG. 16, the reference numeral8001 denotes an ATM cell block sequence constructed of 248 ATM cellblocks of 47 bytes as described in the first preferred embodiment. Thereference numeral 8002 denotes data in which an interleave process useparity and a forward error correction (FEC) use parity (the forwarderror correction use parity referred to as FEC hereinafter) are attachedto the ATM cell block sequence 8001 by a method as described later (SeeFIG. 17). In the data 8002, the hatched sections serve as the Parity forFEC. The reference numeral 8003 denotes a user information region of CSof the AAL layer. The reference numeral 8004 denotes the dataconstruction of the SAR sublayer of the AAL layer (the AAL TYPE 1). Thereference numeral 8005 denotes an ATM layer cell.

The interleave process and the method for adding the Parity for FEC fromthe ATM cell block sequence 8001 to the data 8002 will be described nextwith reference to FIG. 17. In this case, FIG. 17 is a memory map showingstorage contents of an interleave buffer memory 1002 according to aninterleave method executed by the interleave control circuit 1003 ofFIG. 15.

FIG. 17 shows a coding method of the interleave (long interleave)process and an error correcting code coding process prescribed by theadaptation layer (the AAL TYPE 1) of the ATM of the method shown in FIG.2 to FIG. 9 of ITU-T Recommendation I.363 and FIG. 2 to FIG. 9 ofJT-I363.

The method shown in FIG. 17 executes the interleave process by means ofthe interleave buffer memory 1002 having a matrix form, where data writeand read control is expressed by the concept of a two-dimensionalmatrix. At the writing stage, data are written in a unit of 124 bytes (0to 123) in the row direction of the matrix as denoted by 9001, and aparity for FEC 8000 of four bytes (124 to 127) are added to each row.The writing is completed by repeating this process 47 times. The Parityfor FEC 8000 is able to execute error correction to a maximum of twobits by using, for example, Reed-Solomon codes (128 and 124) or correcta loss to a maximum of four bites.

The reading is executed in the column direction of the matrix, andconsequently 128 blocks of 47 bytes (0 to 46) are generated. This resultof read is the data 8002 shown in FIG. 16. The data write and read unitof FIG. 17 is referred to as an interleave unit hereinafter.

In FIG. 16, the ATM cell block sequence 8001 is constructed of 248 ATMcell blocks of 47 bytes, and there are 124 blocks in terms of blocks of47 bytes in the payload section of the matrix shown in FIG. 17.Therefore, the data can be processed in two interleave units withoutexcess nor deficiency. That is, by executing two times the process ofthe interleave unit of FIG. 17, the data of the ATM cell block sequence8001 can be processed without excess nor deficiency while adding nouseless dummy data. The parities for FEC 8000 and 8100 are added in aunit of 47 bytes, and therefore, this method is also appropriate for theprocess of the AAL TYPE 1.

Four blocks of the parities for FEC 8000 and 8001 are added in theinterleave unit, and therefore, the ATM cell block 8002 increases innumber from 248 by 4×2=8 to 256 ATM cell blocks.

The process subsequent to the ATM cell block 8002 in FIG. 16 is similarto that of the method described in the fourth preferred embodimentexcept for the increase in data amount by the parities and theconstruction of a convergence sublayer protocol data unit in theinterleave unit.

The user data information 8003 is divided into two protocol data unitsand transmitted to the SAR layer. In the SAR layer, a 4-bit sequencenumber (SN) and a 1-byte CRC (SNP) or the like for protecting the 4-bitsequence number are added in a unit of 47 bytes according to the AALTYPE 1 protocol and the resulting 48 bytes are transmitted to the ATMlayer. Furthermore, in the ATM layer, as indicated by the hatchedsection 8005, a 5-byte ATM cell header is added for the formation an ATMcell.

It is to be noted that the protocol data unit 8003 merely conceptuallyexists, and actually each ATM cell block 8002 has 47 bytes. Therefore,each ATM cell blocks can also be directly mapped to the layer of thedata block 8004.

FIG. 15 is a block diagram showing a construction of the DIF dataprocessing circuit 104 d according to the fifth preferred embodiment.The present preferred embodiment is constructed by further providing theDIF data processing circuit 104 of FIG. 1 with a parity adding circuit1001, an interleave buffer memory 1002 and an interleave control circuit1003. The block buffer memory 6002 and the block buffer memory controlcircuit 6003 operate in a similar manner to that of the correspondingcircuits 6002 and 6003 of the first preferred embodiment of FIG. 4.

In FIG. 15, the ATM cell block sequence 8001 outputted from the blockbuffer memory 6002 is formed into 128-byte data by adding the 4-byteparities for FEC 8000 and 8100 in a unit of 124 bytes by means of theparity adding circuit 1001 and then outputted.

The interleave buffer memory 1002 is constructed of two memories capableof storing therein the interleave unit shown in FIG. 17 and alternatelyused for the writing and reading. The writing and reading of theinterleave buffer memory 1002 are executed by the interleave controlcircuit 1003. The interleave control circuit 1003 generates an addressso that 128-bytes data from the parity adding circuit 1001 is writteninto the interleave buffer memory 1002 in the row direction 9001 of FIG.17 and executes the writing of the data. When the writing of each row iscompleted, the write operation is advanced in the row direction in adirection in which the column address increases, and the operation isswitched to the reading when the interleave unit shown in FIG. 17becomes full.

On the other hand, for the reading, the interleave control circuit 1003generates an address and sequentially reads the data in a unit of 47bytes so that the data are read out from the interleave buffer memory1002 in the column direction 9002 of FIG. 17, thereby obtaining the data8002.

The interleave control circuit 1003, which repeatedly generates a fixedaddress for interleave, can be constructed of a simple circuit by meansof a ROM in which each address of one sequence is stored.

The data read out from the interleave buffer memory 1002 is outputtedfrom an output terminal 1004. The output data from the output terminal1004 becomes the output of the DIF data processing circuit 104 of FIG.1, and therefore, the next process shifts to the ATM cell formingcircuit 105 of FIG. 1.

The ATM cell forming circuit 105 executes the processing of the AALlayer and the ATM layer. As circuits for these processes, equipments fortransmitting the layers by the AAL TYPE 1 protocol are currentlypopularized, and the circuits can be easily realized by using them. Inregard to the network interface 106, there are popularized ATM physicallayer LSIs and so on, and the network interface can be easily realizedby using them. Therefore, the AAL layer, the ATM layer and the ATMphysical layer can be simply realized at low cost.

As described above, in the fifth preferred embodiment, a data amountreduction of 2.87% can be achieved in a similar manner to that of thefirst preferred embodiment.

When the interleave of the AAL TYPE 1 shown in FIG. 17 is used, the datatransmission amount increase in the interleave unit. Therefore, unlessthe information amount reduction of the DVC subsequence is executed, theprocess in the interleave unit of FIG. 17 must be transmitted threetimes. However, according to the fifth preferred embodiment of thepresent invention, the information amount reduction is executed, andtherefore, the transmission can be achieved by executing the processtwice in the interleave unit of FIG. 17. Therefore, the communicationsload can be remarkably reduced and the use of the resources of thecommunications network can be reduced. By virtue of the reduction in theamount of communications, the communications time is reduced and thereliability of the real-time communications is improved by that much ordegree. Furthermore, by reducing the amount of communications, a loadapplied on an ATM switch and so on inside the network is also reducedand the probability of the cell loss or the like is also reduced, sothat high-quality transmission can be provided.

Furthermore, the Parity for FEC is added after executing the interleaveprocess, and therefore, correction of two symbols and correction of theloss of four symbols can be achieved. Therefore, the correctioneffectively operates also on the cell loss (packet loss) and the biterror, which are the characteristic error of the ATM communications(packet communications), so that communications of a high reliabilitycan be achieved.

Furthermore, based on the processing of the standardized AAL TYPE 1, thecurrently popularized equipments can be used as they are and theconstruction of the circuit to be added is allowed to be very simple, sothat the circuit can be realized very easily at low cost.

Furthermore, the DIF block subsequence and the ATM cell block sequencehave constant amount of information. Therefore, by using the AAL TYPE 1of the ATM transmission protocol appropriate for the transmission ofsound and image at a fixed rate, the reliability of the real-timecommunications is improved. Furthermore, if the error rate of thenetwork is within the range of error correction, then ATM communicationsof highly-reliable DVC (packet data string) can be achieved with asimple construction.

Sixth Preferred Embodiment

FIG. 18 is a block diagram showing a construction of a DIF dataprocessing circuit 104 e according to a sixth preferred embodiment ofthe present invention. This sixth preferred embodiment is a modifiedpreferred embodiment of the third preferred embodiment or a modifiedpreferred embodiment of the fifth preferred embodiment. As shown in FIG.18, this preferred embodiment is characterized in that the block buffermemory control circuit 6003 b of the third preferred embodiment of FIG.10 and a new interleave control circuit 1003 a by means of theinterleave method of FIG. 20 are provided.

The matrix of the interleave buffer memory 1002 of the fifth preferredembodiment of FIG. 17 can store therein valid data information of124×47=5828 bytes. In contrast to this, the data 1802 of FIG. 19 has5780 bytes, which has a shortage of 48 bytes, and therefore, dummy data1805 of 48 bytes are added to the newly formed header of five bytes asdenoted by 1804 in FIG. 19, thereby providing a total of 5828 bytes. Itis to be noted that the position of the dummy data 1805 is not limitedto the position indicated by the transmission unit 1804, and it isacceptable to put header expansion information, a secondly writtenheader or other information into the section of the dummy data 1805. Theadding timing of the dummy data 1805 may be provided at the time ofbeing written into the matrix of the interleave buffer memory 1002.

FIG. 20 is a memory map showing storage contents of the interleavebuffer memory 1002 according to an interleave method executed by theinterleave control circuit 1003 a of FIG. 18. That is, FIG. 20 shows thememory map of the interleave buffer memory 1002 when the data 1804 ofFIG. 19 is written in the interleave unit of FIG. 17. In this case, thewriting is executed in the row direction 9001 of the matrix of FIG. 20,and therefore, 5-byte header and 48-byte dummy data are written into thehead of the first row of the matrix of FIG. 20. Subsequently, data aresequentially written in the row direction, and when the writing of datainto each row is completed, writing of data in the row direction of thenext column is executed. As shown in FIG. 19, the transmission unit 1804has a total of 5828 bytes, and therefore, the transmission unit isstored in the interleave unit into the matrix of FIG. 20 without excessnor deficiency. Reading is executed in a unit of 47 bytes in the columndirection of the matrix of FIG. 20 as described above. Thereafter, theATM cell formation process is executed as denoted by 8003, 8004 and 8005in FIG. 16, and the resulting data is finally transmitted as an ATMcell.

The circuit of the sixth preferred embodiment can be constructed bycombining the DIF data processing circuit 104 b of the third preferredembodiment of FIG. 10 with the DIF data processing circuit 104 d of thefifth preferred embodiment of FIG. 15, and the block buffer memorycontrol circuit 6003 b and the interleave control circuit 1003 a areemployed in this case. Then, according to the sixth preferredembodiment, an effect similar to that of the fifth preferred embodimentis obtained.

The subject matter of the sixth preferred embodiment of the presentinvention is to obtain a reduction effect by reducing the times oftransmission (two times in the fifth preferred embodiment and the sixthpreferred embodiment) in a unit of matrices through reduction in theamount of information from the number of times of transmission (threetimes in the fifth preferred embodiment and the sixth preferredembodiment) in a unit of matrices, which must be transmitted when apredetermined unit of data amount (subsequence in the present preferredembodiment) is mapped directly on the matrix in the case where data thatis conceptually theoretically arranged in a matrix form is transmittedby an interleave means with an error correcting means provided.Therefore, although the present preferred embodiment has been describedby the method standardized as an option of the AAL TYPE 1 shown in FIG.17 as the interleave and error correction methods, the present preferredembodiment is not limited to this method.

Seventh Preferred Embodiment

FIGS. 21(A)-21(E) are views showing a construction of a seventhpreferred embodiment of the present invention, wherein FIG. 21(A) is ablock diagram showing a construction of the DIF data processing circuit104 f of the seventh preferred embodiment, FIG. 21 (B) is a blockdiagram showing data inputted from the block buffer memory 6002 to theinterleave buffer memory 3000 of FIG. 21(A), FIG. 21(C) is a memory mapshowing storage contents of the interleave buffer memory 3000 accordingto an interleave method executed by the interleave control circuit 3001of FIG. 21(A), FIG. 21(D) is a block diagram showing data inputted fromthe parity adding circuit 3002 to the interleave buffer memory 3003 ofFIG. 21(A) and FIG. 21(E) is a memory map showing storage contents ofthe interleave buffer memory 3003 according to an interleave methodexecuted by the interleave control circuit 3004 of FIG. 21(A).

This seventh preferred embodiment is a modified preferred embodiment ofthe sixth preferred embodiment and is characterized in that the DIF dataprocessing circuit 104 b of the third preferred embodiment of FIG. 10 isfurther provided with an interleave buffer memory 3000, an interleavecontrol circuit 3001, a parity adding circuit 3002, an interleave buffermemory 3003 and an interleave control circuit 3004 as shown in FIG.21(A). In particular, the preferred embodiment is characterized in thata transmission system which is more tolerant of errors and is moreappropriate for the DVC transmission system than the third aspect of thepresent invention as shown in the fifth preferred embodiment and thesixth preferred embodiment that use the long interleave and the errorcorrection system described with reference to FIG. 17 is provided.

The DIF data processing circuit 104 f of the seventh preferredembodiment is provided with:

(a) an interleave control circuit 3001 that executes a first interleaveprocess by writing the data string outputted from the block buffermemory 6002 into an interleave buffer memory 3000 having a first matrixform in a first direction (write direction of FIG. 21(C)) of the firstmatrix, and thereafter, reading the data from the interleave buffermemory 3000 in a second direction (read direction of FIG. 21(C))perpendicular to the first direction of the first matrix, and then,outputs the data obtained after the first interleave process in a unitof data in the second direction;

(b) a parity adding circuit 3002 that adds a predetermined Parity forFEC to the data outputted from the interleave buffer memory 3000 in aunit of data in the second direction, and then, outputs the data towhich the Parity for FEC is added; and

(c) an interleave control circuit 3004 that executes a second interleaveprocess by writing data outputted from the parity adding circuit 3002into the interleave buffer memory 3003 having a second matrix form in afourth direction (write direction of FIG. 21(E)) of the second matrixcoinciding with the second direction of the first matrix, andthereafter, reading the data from the interleave buffer memory 3003 in athird direction (read direction of FIG. 21(E)) perpendicular to thefourth direction of the second matrix, and then, outputs the dataobtained after the second interleave process in a unit of data in thethird direction.

For example, it is sometimes the case where cell loss (burst cell loss)continuously occurs in the ATM transmission line of a degraded qualityand goes beyond the error correction capacity of the ATM transmissionapparatus by means of the parity shown in FIG. 20 or FIG. 17. Forexample, in the case where the cell 1901 shown in FIG. 20 becomes one ofcells that cannot be corrected and if part of the data of the DIF blockis included in the cell 1901, then all the DIF block data become errorsaccording to the method as described in the sixth preferred embodiment.

FIG. 22 is a block diagram showing an error distribution when cell lossoccurs in the ATM transmission apparatus provided with the DIF dataprocessing circuit 104 f of FIG. 21. In FIG. 22, DIF block numbers areprovided above the DIF blocks. In this case, the DIF block numbers are 0to 74 numbering 75 DIF blocks included in the transmission unit 1804 ofFIG. 19 from the head, and the byte numbers are 0 to 76 numbering the77-byte DIF blocks shown in FIG. 19 from the head. In FIG. 22, theerrors included in the DIF blocks are indicated by the black lines. Asshown in FIG. 22, if the cell 1901 cannot be corrected, then the headerand the 46 DIF blocks include errors.

This case has the problem that the processing of DVC is executed in aunit of macro blocks shown in FIG. 3 and only one error status (STA) isowned by the macro block as described above. Therefore, if each DIFblock (macro block) has at least one byte of error, then the whole DIFblock is treated as an error. Therefore, 46 DIF blocks become errors inFIG. 22.

In FIG. 22, concrete errors exist in the third byte (byte number 2) ofthe header, the byte number 73 of the DIF block number 0, the bytenumber 43 of the DIF block number 2, the byte number 13 of the DIF blocknumber 4, the byte number 60 of the DIF block number 5, the byte number30 of the DIF block number 7, the byte number 0 of the DIF block number9, the byte number 47 of the DIF block number 10, the byte number 17 ofthe DIF block number 12, the byte number 64 of the DIF block number 13,the byte number 34 of the DIF block number 15, the byte number 4 of theDIF block number 17, the byte number 15 of the DIF block number 18, thebyte number 21 of the DIF block number 20, the byte number 68 of the DIFblock number 21, the byte number 38 of the DIF block number 23, the bytenumber 8 of the DIF block number 25, the byte number 55 of the DIF blocknumber 26, the byte number 25 of the DIF block number 28, the bytenumber 72 of the DIF block number 29, the byte number 42 of the DIFblock number 31, the byte number 12 of the DIF block number 33, the bytenumber 59 of the DIF block number 34, the byte number 29 of the DIFblock number 36, the byte number 76 of the DIF block number 37, the bytenumber 46 of the DIF block number 39, the byte number 16 of the DIFblock number 41, the byte number 63 of the DIF block number 42, the bytenumber 33 of the DIF block number 44, the byte number 3 of the DIF blocknumber 46, the byte number 50 of the DIF block number 47, the bytenumber 20 of the DIF block number 49, the byte number 67 of the DIFblock number 50, the byte number 37 of the DIF block number 52, the bytenumber 7 of the DIF block number 54, the byte number 54 of the DIF blocknumber 55, the byte number 24 of the DIF block number 57, the bytenumber 71 of the DIF block number 58, the byte number 41 of the DIFblock number 60, the byte number 11 of the DIF block number 62, the bytenumber 58 of the DIF block number 63, the byte number 28 of the DIFblock number 65, the byte number 75 of the DIF block number 66, the bytenumber 45 of the DIF block number 68, the byte number 15 of the DIFblock number 70, the byte number 62 of the DIF block number 71 and thebyte number 32 of the DIF block number 73.

As described above, when one arbitrary cell loss cannot be corrected,the error propagates, consequently significantly disturbing the image.This is unacceptable in the field of, for example, broadcasting stationsrequiring a high image quality.

Substantially, the above problem is attributed to the ATM cell finallyprocessed so that the direction thereof is processed to be perpendicularto the direction of the DIF block data string through the longinterleave (FIG. 20) of the AAL TYPE 1. If the error correction capacityis improved, then the above problem will occur when the error goesbeyond the error correction capacity. If the error correction is notexecuted, then the problem will become more serious.

In view of the above problem, this seventh preferred embodiment solvesthe problem by using the long interleave of the AAL TYPE 1 which iscurrently the mainstream as the standard and of which the equipments arepopularized at low cost and processing the upper layer of the longinterleave (See FIG. 20) of the AAL TYPE 1, thereby making the directionof the DIF block data string coincide with the direction of the ATM cellthat is practically used as a transmitting means.

FIGS. 23(A) and 23(B) are views showing an interleave method of the DIFdata processing circuit 104 f of FIG. 21(A), wherein FIG. 23(A) is amemory map showing storage contents of the interleave buffer memory 3000according to the interleave method executed by the interleave controlcircuit 3001 of FIG. 21(A) and FIG. 23(B) is a memory map showingstorage contents of the interleave buffer memory 3003 according to theinterleave method executed by the interleave control circuit 3004 ofFIG. 21(A).

The reference numeral 2100 shown in FIG. 23(A) denotes the process inthe upper layer of the long interleave for canceling the long interleaveof the AAL TYPE 1 to be executed by the interleave buffer memory 3000.The reference numeral 2101 shown in FIG. 23(B) denotes the longinterleave of the AAL TYPE 1 to be executed by the interleave buffermemory 3000 and is the same processing as in FIG. 20 (or FIG. 17).

In FIG. 23(A) and FIG. 23(B), the data processed in the interleave unitare numbered from 0 to 5827. The numbers 0, 1, 2, . . . , 5827 indicatethe direction of the data string of the DIF block indicated by, forexample, the transmission unit 1804 of FIG. 19.

As shown in FIG. 23(A), the data string 1804 is written in the columndirection into the interleave buffer memory 3000, and then is read outfrom the interleave buffer memory 3000 in the row direction. As shown inFIG. 23(B), the read data is written into the interleave buffer memory3003 in the row direction, and then, is read out from the interleavebuffer memory 3003 in the column direction in conformity to the longinterleave standard (FIG. 17). The read direction from the interleavebuffer memory 3000 becomes the ATM cell direction, and consequently theDIF block direction and the ATM cell direction coincide with each other.

FIG. 24 is a memory map showing the detail of the storage contents ofthe interleave buffer memory 3003 according to the interleave methodexecuted by the interleave control circuit 3004 of FIG. 21(A). FIG. 24illustrates in more detail the same thing as 2101 of FIG. 23. FIG. 24illustrates an example in which the transmission unit 1804 of FIG. 19 isstored, where the data string 1804 is stored from the head via theheader, dummy, subsequent DIF block 0, DIF block 1, . . .

It is now assumed that, for example, cell loss that cannot be correctedoccurs in a position 2200 identical to the position described withreference to FIG. 20. In this case, the direction of the transmissionunit 1804 coincides with the direction of the ATM cell, and therefore,the ATM cell 2200 includes only part of the DIF block 0 and part of theDIF block 1. The data block diagram of the data string 1804 in this caseis shown in FIG. 25. FIG. 25 shows the error cell (ATM cell 2200) by thecross hatching. In this example, only the two DIF blocks of the DIFblock 0 and the DIF block 1 have errors.

As described above, according to the seventh preferred embodiment, theerror propagation can be suppressed to the minimum even when anuncorrectable cell loss occurs, thereby allowing a high image quality tobe maintained. It is to be noted that the macro block that becomes anerror can be made less conspicuous by being corrected by the previousframe or the like.

FIG. 21(A) shows the construction of the DIF data processing circuit 104f of the seventh preferred embodiment. In FIG. 21(A), a DIF block datastring is inputted via the input terminal 6001. In FIG. 21(A), a DIFblock data string as denoted by 1804 in FIG. 11 is first of all obtainedby the block buffer memory 6002 and the block buffer memory controlcircuit 6003 b of FIG. 4 similar to those of the third preferredembodiment. In this case, the block diagram of the data outputted fromthe block buffer memory 6002 is shown in FIG. 21(B). This is the same asthe transmission unit 1804 of FIG. 11.

The interleave buffer memory 3000 has a storage capacity for storingtherein the data 2100 of FIG. 23, and the data outputted from the blockbuffer memory 6002 is written in the column direction into theinterleave buffer memory 3000 while shifting the column from the left tothe right of the figure in terms of the conception of a two-dimensionalmatrix as shown in FIG. 21(C). For the reading, the data is read in therow direction while shifting the row from the upside to the downside ofthe figure. The write and read control of the interleave buffer memory3000 is executed by the interleave buffer memory control circuit 3001.These are the fixed write and read methods, and therefore, the methodscan be easily implemented by storing a program of the methods in, forexample, a ROM of a small storage capacity and providing the interleavecontrol circuit 2601 with the ROM.

The conceptual view of the data written in the interleave buffer memory3000 is shown in FIG. 21 (C). This corresponds to the data 2100 of FIG.23(A). The data outputted from the interleave buffer memory 3000 istransmitted to the parity adding circuit 2602, and a parity for FEC isadded to the 124-byte data. The block diagram of the data is shown inFIG. 21(D).

The data outputted from the parity adding circuit 3002 is written intothe interleave buffer memory 3003. For the writing, data are written inthe row direction while shifting the row from the upside to the downsideof the figure in terms of the conception of the two-dimensional matrixas shown in FIG. 21(E). For the reading, the data are read in the columndirection while shifting the column from the left to the right of thefigure.

The write and read control of the interleave buffer memory 3003 isexecuted by the interleave buffer memory control circuit 3004. These arethe fixed write and read methods, and therefore, the methods can beeasily implemented by storing a program of the methods in, for example,a ROM of a small storage capacity and providing the interleave controlcircuit 3004 with the ROM.

The block diagram of the data written in the interleave buffer memory3003 is shown in FIG. 21 (E). This corresponds to the data 2101 of FIG.23. The data outputted from the interleave buffer memory 3003 isoutputted via an output terminal.

The processing of the AAL TYPE 1 is executed by the ATM cell formingcircuit 105 similar to the description of the fifth preferredembodiment. In this case, a sequence number SN and a sequence numberprotection SNP are added, and thereafter, the processed data packet istransmitted to the ATM network 100 via the network interface 106.

As shown in FIG. 17, the above has described the case where the datastring is divided into 124 packets as a lower layer, an error correctingcode is added and a second packet of 47 is formed in the seconddirection when i=124 and j=47.

As described above, according to the seventh preferred embodiment, thecell loss and bit error within the error correction capacity arecorrected by the error correction, and even if the cell loss and the biterror beyond the error correction capacity occur, the error does notpropagate. Accordingly, high-quality image and sound transmissiontolerant of the cell loss and bit error can be provided.

Although the seventh preferred embodiment has been described taking thecase where the DIF data string 1804 of FIG. 19 is transmitted as anexample, the execution of data deletion is not the subject matter of thepresent invention. By making the direction of the data string (DIF blockdata string) coincide with the direction of the packet (ATM cell) thatis actually transmitted, the error propagation can be suppressed to theminimum for the obtainment of an effect. Therefore, even the case whereno data deletion is executed is not excluded from the scope of thepresent invention.

The seventh preferred embodiment is based on the example in which thedata 1901 of FIG. 20 cannot be corrected and the error propagates to aplurality of DIF blocks. However, this is the example in which theerrors go beyond the error correction range due to a burst-like cellloss. It is sometimes the case where cell loss continuously occurs inthe ATM when the network is congested, and the present invention leadsto very great effect when used.

Eight Preferred Embodiment

FIGS. 26(A)-26(F) are views showing a construction of an eighthpreferred embodiment of the present invention, wherein FIG. 26(A) is ablock diagram showing a construction of the DIF data processing circuit104 g of the eighth preferred embodiment, FIG. 26(B) is a block diagramshowing data inputted from the block buffer memory 6002 to the CRCadding circuit 3106 of FIG. 26(A), FIG. 26(C) is a block diagram showingdata inputted from the CRC adding circuit 3106 to the interleave buffermemory 3000 of FIG. 26(A), FIG. 26(D) is a memory map showing storagecontents of the interleave buffer memory 3000 according to theinterleave method executed by the interleave control circuit 3001 ofFIG. 26(A), FIG. 26(E) is a block diagram showing data inputted from theparity adding circuit 3002 to the interleave buffer memory 3003 of FIG.26(A) and FIG. 26(F) is a memory map showing storage contents of theinterleave buffer memory 3003 according to the interleave methodexecuted by the interleave control circuit 3004 of FIG. 26(A).

This eighth preferred embodiment is a modified preferred embodiment ofthe seventh preferred embodiment, and as shown in FIG. 26(A), thepreferred embodiment is characterized in that a CRC adding circuit 3106and a CRC addition control circuit 3107 are further inserted between theblock buffer memory 6002 and the interleave buffer memory 3000 ascompared with the DIF data processing circuit 104 f of FIG. 21(A). Inthis case, the CRC adding circuit 3106 adds a parity for error detectionto the data string outputted from the block buffer memory 6002 in adirection in which the data string is aligned, and then, outputs thedata string to which the parity for error detection is added in apredetermined unit of data.

In this eighth preferred embodiment, a transmission system for providingthe transmission system of a higher image quality than those of thetransmission system by the long interleave of the AAL TYPE 1 and theerror correction and the transmission system for executing a similarerror correction will be described. That is, a transmission system thatcopes with not only the cell loss but also the bit error is provided.

The description of the preferred embodiment is based on an example ofthe transmission system by the long interleave of the AAL TYPE 1 and theerror correction. It is to be noted that the execution of the longinterleave itself is not the subject matter of the present invention,and the present invention is effective for the transmission systemprovided with a system for correcting errors in a predetermined unit.Therefore, the scope of the present invention excludes neither one ofthe case where the long interleave is executed, the case where the longinterleave is not executed and even the case where a process forcanceling the long interleave in the upper layer of the long interleaveof the AAL TYPE 1 as described in the seventh preferred embodiment.

FIG. 27 is a memory map showing storage contents of the interleavebuffer memory 3003 according to an interleave method executed by the DIFdata processing circuit 104 g of FIG. 26(A). The interleave unitillustrated in FIG. 27 is identical to the above-mentioned longinterleave unit of FIG. 17. In FIG. 27, an error correcting code isadded in the row direction (longitudinal direction in the figure) of thematrix of the interleave buffer memory 3003, and therefore, double errorcorrection and quadruple loss correction can be technically achieved.

In the ATM transmission system, the cell loss meaning the loss of an ATMcell during the transmission, the bit error in the optical fiber cableor a twisted pair cable or the like occurs. In particular, with regardto the cell loss, there is a high probability of the occurrence of anerror due to the cell loss of continuous cells when the network iscongested. In particular, in the case of transmission based on thestandard of the AAL TYPE 1, each ATM cell is transmitted with a sequencenumber added thereto. Therefore, by checking their continuity on thereceiving side, it is enabled to identify the lost cell and the positionof the cell (cell loss).

Referring to FIG. 27, each column is the payload of the ATM cell, whichis transmitted with one byte of the sequence number (SN of FIG. 14) forthe formation of 48 bytes and five bytes of the ATM cell headerattached. Therefore, if, for example, the cell 2704 of FIG. 27 is lost,then the position can be identified by the check of the continuity ofthe cells. If there are not more than two cases of cell loss and biterror, the position and error can be detected and corrected by the 4-itparity even though the position of cell loss and bit error cannot befound.

However, when not less than four cases of cell loss occur, although theposition of the cell loss can be found by the above-mentioned check ofcontinuity of cells, the presence or absence of the bit error cannot bedetected. Accordingly, there is the possibility of the occurrence oferroneous correction if loss correction is executed. When not less thanfive cases of cell loss occur, the loss correction cannot be executeddue to a shortage of parity capacity.

Generally speaking, the probability of the occurrence of bit error isextremely smaller than the probability of the occurrence of cell loss.Therefore, if, for example, the cells 2704 and 2708 are lost, there is ahigh probability of the inclusion of a bit error in the other cells.However, the bit error exists even with little probability, andtherefore, if an image is displayed on a screen with a bit error missed,then incorrect data is outputted onto the screen, causing a significantdeterioration of the image quality.

Furthermore, when the cells 2704 and 2707 are errors in FIG. 27, thereis very little probability of the inclusion of a bit error in the othercells. However, so long as there is a probability of the inclusion of abit error, this results in an erroneous correction if the losscorrection is effected on the error cell, so that an incorrect image isconsequently displayed on the screen, resulting in a destroyed image.

In the eighth preferred embodiment, the presence or absence of the biterror is surely detected, so that the DIF blocks including no bit errorare outputted as they are, thereby utilizing the greater part of dataand treating each DIF block including a bit error as an error. Forexample, by treating the status bit (SAT) of FIG. 3 as an error, theerror correcting process is executed to allow a high image quality and ahigh sound quality to be maintained.

For the above purpose, the eighth preferred embodiment of the presentinvention executes error check by CRC in the ATM cell transmissiondirection. The example shown in FIG. 27 adopts 8-bit CRC (one byte) byassigning one CRC to the header and assigning one CRC to two DIF blocks.It is to be noted that one CRC is assigned to one DIF block for the lastDIF block. The assignment of CRC is not limited to this, and whenassigning CRC to an ATM cell, the scope of the present invention doesnot exclude the assignment of an arbitrary number of CRCs as in the casewhere one CRC is assigned to one DIF block.

In FIG. 27, one-byte CRC is added next to the 5-byte header, which isfollowed by nine bytes of dummy bit and a one-byte CRC added to everytwo DIF blocks. It is to be noted that a CRC is assigned to one DIFblock for the last DIF block. In FIG. 27, the CRCs are painted in black.

In FIG. 27, the concrete CRC positions are as follows. The 6th byte ofthe 1st column is used as the CRC for the header. The 29th byte of the4th column is used as the CRC for the DIF block 0 and the DIF block 1.The 43rd byte of the 7th column is used as the CRC for the DIF block 2and the DIF block 3. The 10th byte of the 11th column is used as the CRCfor the DIF block 4 and the DIF block 5. The 24th byte of the 14thcolumn is used as the CRC for the DIF block 6 and the DIF block 7. The38th byte of the 17th column is used as the CRC for the DIF block 8 andthe DIF block 9. The 5th byte of the 21st column is used as the CRC forthe DIF block 10 and the DIF block 11. The 19th byte of the 24th columnis used as the CRC for the DIF block 12 and the DIF block 13. The 33rdbyte of the 27th column is used as the CRC for the DIF block 14 and theDIF block 15. The 47th byte of the 30th column is used as the CRC forthe DIF block 16 and the DIF block 17. The 14th byte of the 34th columnis used as the CRC for the DIF block 18 and the DIF block 19. The 28thbyte of the 37th column is used as the CRC for the DIF block 20 and theDIF block 21. The 42nd byte of the 40th column is used as the CRC forthe DIF block 22 and the DIF block 23. The 9th byte of the 44th columnis used as the CRC for the DIF block 24 and the DIF block 25. The 23rdbyte of the 47th column is used as the CRC for the DIF block 26 and theDIF block 27. The 37th byte of the 50th column is used as the CRC forthe DIF block 28 and the DIF block 29. The 4th byte of the 54th columnis used as the CRC for the DIF block 30 and the DIF block 31. The 18thbyte of the 57th column is used as the CRC for the DIF block 32 and theDIF block 33. The 32nd byte of the 60th column is used as the CRC forthe DIF block 34 and the DIF block 35. The 46th byte of the 63rd columnis used as the CRC for the DIF block 36 and the DIF block 37. The 13thbyte of the 67th column is used as the CRC for the DIF block 38 and theDIF block 39. The 27th byte of the 70th column is used as the CRC forthe DIF block 40 and the DIF block 41. The 41st byte of the 73rd columnis used as the CRC for the DIF block 42 and the DIF block 43. The 8thbyte of the 77th column is used as the CRC for the DIF block 44 and theDIF block 45. The 22nd byte of the 80th column is used as the CRC forthe DIF block 46 and the DIF block 47. The 36th byte of the 83rd columnis used as the CRC for the DIF block 48 and the DIF block 49. The 3rdbyte of the 87th column is used as the CRC for the DIF block 50 and theDIF block 51. The 17th byte of the 90th column is used as the CRC forthe DIF block 52 and the DIF block 53. The 31st byte of the 93rd columnis used as the CRC for the DIF block 54 and the DIF block 55. The 45thbyte of the 96th column is used as the CRC for the DIF block 56 and theDIF block 57. The 12th byte of the 100th column is used as the CRC forthe DIF block 58 and the DIF block 59. The 26th byte of the 103rd columnis used as the CRC for the DIF block 60 and the DIF block 61. The 40thbyte of the 106th column is used as the CRC for the DIF block 62 and theDIF block 63. The 7th byte of the 110th column is used as the CRC forthe DIF block 64 and the DIF block 65. The 21st byte of the 113th columnis used as the CRC for the DIF block 66 and the DIF block 67. The 35thbyte of the 116th column is used as the CRC for the DIF block 68 and theDIF block 69. The 2nd byte of the 120th column is used as the CRC forthe DIF block 70 and the DIF block 71. The 16th byte of the 123rd columnis used as the CRC for the DIF block 72 and the DIF block 73. The 47thbyte of the 124th column is used as the CRC for the DIF block 74.

It is proper to execute the data write and read in FIG. 27 conceptuallyin the column direction (longitudinal direction in FIG. 27) of thematrix of the interleave buffer memory 3003. That is, if the DIF blockdata is written in the column direction, and thereafter, read in thecolumn direction on the matrix shown in FIG. 27, then the invention asdescribed in the seventh preferred embodiment may be applied accordingto the preceding processing. In this case, it is proper for the datastring to have a sequence of the header (5 bytes), header use CRC (1byte), dummy (9 bytes), DIF block 0 (77 bytes), DIF block 1 (77 bytes),CRC (1 byte) for DIF block 0 and DIF block 1, DIF block 2 (77 bytes),DIF block 3 (77 bytes), CRC (1 byte) for DIF block 2 and DIF block 3,DIF block 4 (77 bytes), . . . , DIF block 74 (77 bytes) and CRC (1 byte)for DIF block 74.

FIG. 28 is a block diagram showing a packet block generating methodexecuted by an ATM transmission apparatus provided with the DIF dataprocessing circuit 104 g of FIG. 26(A).

In FIG. 26(A), the DIF block data string is inputted via an inputterminal. Next, based on the inputted data string, the block buffermemory 6002 and block buffer memory control circuit 6003 a obtain theDIF block data string that is shown in FIG. 26(B) and denoted by 2900 inFIG. 28, and then, output the data string. The construction of the dataoutputted from the block buffer memory 6002 is shown in FIG. 26(B). Thisis identical to 2900 of FIG. 28. The data string 2900 shown in FIG.26(B) differs from the data string 1804 of FIG. 19 only in the number ofbytes of the dummy. Therefore, the circuit can be easily realized bymerely slightly changing the block buffer memory control circuit 6003 bof FIG. 10.

The CRC adding circuit 3106 is a circuit for adding an 8-bit CRC to thedata string outputted from the block buffer memory 6002, and theoperation thereof is controlled by the CRC addition control circuit3107. The CRC addition control circuit 3107 executes a CRC addingprocess by controlling the CRC adding circuit 3106 with regard to thereset timing of the CRC adding circuit, the CRC adding timing, a dummyadding timing and so on.

According to the CRC adding method, the CRC addition control circuit3107 resets the CRC adding circuit 3106 at the head of the header andadds one byte of CRC to the tail of the 5-byte header. The CRC addingcircuit 3106 is reset at the head of the DIF block 0, and 1-byte CRC isadded next to the DIF block 1. Likewise, the CRC adding circuit 3106 isreset for the DIF blocks of the even numbers, 1-byte CRC is added behindthe DIF blocks of the odd numbers, and the 1-byte CRC is added to everytwo DIF blocks. A CRC is added to one DIF block for only the last DIFblock.

The CRC addition control circuit 3107 resets the CRC adding circuit 3106in accordance with the above-mentioned reset timing to execute controlso as to output eight bits (one byte) of CRC from the CRC adding circuit3106 in accordance with the CRC adding timing. The output data of theCRC adding circuit 3106 is shown in FIG. 26(C) FIG. 26(C) is identicalto 2902 of FIG. 21.

Subsequently, the interleave buffer memory 3000, interleave buffermemory control circuit 3001, parity adding circuit 3002, interleavebuffer memory 3003 and interleave control buffer memory circuit 3004have the same processes as those of the seventh preferred embodiment ofFIG. 21.

As described above, according to the eighth preferred embodiment of thepresent invention, the cell loss and bit error are corrected by errorcorrection within the error correction range. When cell loss or biterror out of the error correction range occurs, the presence or absenceof the bit error is securely detected by the CRC, and the DIF blocksincluding no bit error are outputted as they are for the utilization ofthe greater part of the data. Any DIF block including a bit error istreated as an error and subjected to error correction, thereby allowinga transmission system maintaining a high image quality and a high soundquality to be provided.

Although the eighth preferred embodiment has been described by means ofthe data reducing means shown in FIG. 28, the subject matter of thepresent invention is to provide a CRC adding means (CRC adding circuit3106) in the direction identical to that of the data string to betransmitted and obtain an effect by adding the error correcting code inthe directions perpendicular to each other conceptually on thetwo-dimensional matrix. Therefore, the present invention has an effectregardless of the presence or absence of the data reducing means, andthe scope of the present invention does not exclude even the case whereno data reducing means is provided.

Although the eighth preferred embodiment takes the case where the AALTYPE 1 of the ATM is used as an example, the present invention can berealized by incorporating header information into a varied protocol dataunit (PDU) when using the AAL TYPE 5.

Ninth Preferred Embodiment

FIGS. 29(A)-29(E) are views showing a construction of a ninth preferredembodiment of the present invention, wherein FIG. 29(A) is a blockdiagram showing a construction of the DIF data processing circuit 104 hof the ninth preferred embodiment, FIG. 29(B) is a block diagram showingdata inputted from the block buffer memory 6002 to the interleave buffermemory 3000 of FIG. 29(A), FIG. 29(C) is a memory map showing storagecontents of the interleave buffer memory 3000 according to an interleavemethod executed by the interleave control circuit 3001 of FIG. 29(A),FIG. 29(D) is a block diagram showing data inputted from the parityadding circuit 3002 to the interleave buffer memory 3003 of FIG. 29(A)and FIG. 29(E) is a memory map showing storage contents of theinterleave buffer memory 3003 according to an interleave method executedby the interleave control circuit 3004 of FIG. 29(A).

This ninth preferred embodiment is a modified preferred embodiment ofthe seventh preferred embodiment, and as shown in FIG. 29(A), thepreferred embodiment is characterized in that a block buffer memorycontrol circuit 6003 c is provided as compared with the DIF dataprocessing circuit 104 f of FIG. 21. In this case, the block buffermemory control circuit 6003 c is characterized in generating twotransmission headers having a new identifier by reducing thepredetermined redundancy information from the block informationbelonging to a plurality of blocks based on the data string inputted viathe input terminal 6001, then outputs data including the transmissionunit having the generated two transmission headers and arranges theabove two transmission headers in the data including the abovetransmission unit so that the two transmission headers are positioned atthe head of the data unit in the column direction of the matrix of theinterleave buffer memory 3003 of FIG. 30. These features are providedfor the protection of the header information.

FIG. 30 is a memory map that shows a packet block generating methodexecuted by the DIF data processing circuit 104 h of FIG. 29(A) andshows the detail of the storage contents stored in the interleave buffermemory 3003 of FIG. 29(A). In the ninth preferred embodiment, the headeris protected by transferring two times the header information includingthe time code through the long interleave of the AAL TYPE 1.

As described above, when the cell loss rate and the error rate of theATM network are extremely bad, it is sometimes the case where the cellloss or the like goes beyond the error correction capacity and nocorrection can be effected. For example, in FIG. 24, if the ATM cell2201 is lost and no correction can be executed, since the ATM cell 2201includes the header information of time code information and so on, theposition of the image to which all of the 75 DIF blocks belonging to thelong interleave unit belong cannot be identified, then all the 75 DIFblocks are to be consequently treated as errors, resulting in aremarkably deteriorated image. In particular, when a high image qualityis required by a broadcasting station or the like, the image cannot beaccepted. Therefore, in the preferred embodiment of the presentinvention, the detection probability of the header information in theinterleave unit is improved by incorporating the header information intotwo ATM cells in each interleave unit.

As shown in FIG. 30(A), header information is incorporated into the headsections of an ATM cell 2400 and an ATM cell 2401. In order toincorporate the header information into the positions, the header anddummy information are to be arranged as shown in FIG. 30(B) in thetransmission unit 1804 of FIG. 19.

Although the ninth preferred embodiment has two pieces of headerinformation, the header information is not limited in number to two. Thepositions in which the plurality of headers are stored may be located inany ATM cells so long as the ATM cells are different. The header insideeach ATM cell may be located in an arbitrary position.

As described above, the present preferred embodiment is a modifiedpreferred embodiment of the seventh preferred embodiment, and thedifference to the seventh preferred embodiment is that this preferredembodiment can be realized by executing control so that the header istransmitted two times to the dummy section as shown in FIG. 30(B) bymeans of the block buffer memory control circuit 6003 c of FIG. 29. Inthis case, the time code can be easily realized by providing a registerinside the block buffer memory 6002 and storing the time code in theregister. In a similar manner to that of the seventh preferredembodiment, the processing of the block buffer memory control circuit6003 c is fixed, and therefore, this preferred embodiment can be easilyrealized by providing a ROM inside the block buffer memory controlcircuit 6003 c.

According to the present invention, the data are transmitted by mountingthe plurality of cells with the header of the time code information orthe like for the data in the predetermined processing unit (in theinterleave unit of the AAL TYPE 1 in the ninth preferred embodiment), sothat the image position or sound position in the processing unit can besecurely detected, thereby allowing high-quality image and sound to betransmitted.

Although the ninth preferred embodiment has been described taking thecase where the time code is incorporated two times through the datareducing process shown in FIG. 19 as an example, the subject matter ofthe present invention is to allow the obtainment of the characteristiceffect by writing the time code into the plurality of different packets(ATM cells) inside the transmission process unit (interleave unit of theAAL TYPE 1). Therefore, the present invention has the characteristiceffect regardless of the presence or absence of the data reducingprocess, and the scope of the present invention does not exclude eventhe case where no data reducing process is executed.

As described above, according to the ninth S preferred embodiment of thepresent invention, the header information of the time code or the likecan be surely detected even when the cell loss or bit error occurs, sothat the position of the transmitted image information can be surelydetected, thereby allowing the transmission of the high-quality imageand sound to be achieved.

Tenth Preferred Embodiment

FIG. 31 is a block diagram showing a construction of an ATM transmissionapparatus 1 b according to a tenth preferred embodiment of the presentinvention. FIG. 32 is a block diagram showing an ATM cell formationprocess executed by the ATM cell forming circuit 105 a of FIG. 31.

This tenth preferred embodiment is characterized in that the ATM cellforming circuit 105 a is provided as compared with the first preferredembodiment of FIG. 1 and transmission is executed by means of theprotocol of the AAL TYPE 5 of the ATM.

In FIG. 32, the reference numeral 1101 denotes an ATM cell blocksequence described in the first preferred embodiment. The referencenumeral 1102 denotes an AAL layer CS user information and additionalinformation. The additional information of the AAL TYPE 5 is constructedof:

(a) padding (not shown, referred to as PAD hereinafter) of 0 to 47 bytesfor such adjustment that the frame becomes the multiple of 48 bytes;

(b) CPCS (Common Part Convergence Sublayer) interuser information(CPCS-UU) for transferring information to be used for the upper layer;

(c) common part indicator (CPI) that currently has no predetermined useand set to zero in every case under present conditions;

(d) Length for indicating a user information length in a unit of bytes;and

(e) an error detection use code (CRC-32) of four bits (32 bites) forexecuting error detection of the whole CPCS frame. Eight bytes of theabove CPCS-UU, CPI, Length and CRC-32 are referred to as a trailer inthe following description.

The tenth preferred embodiment of the present invention has a relevanceto the user information region, PAD and Length. According to thestandard of the AAL TYPE 5 protocol, the PAD must be inserted forachieving the adjustment so that a total of the user information regionand the additional information comes to have the multiple of 48 bytes.The PAD is meaningless data, which causes an increase in the amount ofdata to be transmitted, must be made as small as possible. Wheninserting the PAD, it is inserted between the user information regionand the CPCS-UU

The reference numeral 1103 denotes the data construction of SAR(Segmentation and Re-assembly) sublayer of the AAL layer. The referencenumeral 1104 denotes the cell of the ATM layer. The reference numeral1101 denotes data constructed of 248 ATM cell blocks of 47 bytes asdescribed in the first preferred embodiment.

In the CS, user information is constructed of eight ATM cell blocks. Inthis case, the user information comes to have 376 bytes, and therefore,the Length stores therein the state of being 376 bytes. The additionalinformation has eight bytes, and therefore, this results in a total of384 bytes, which is the multiple of 48 bytes of the payload, requiringno useless PAD. When the processing of the data 1102 is completed, thedata is transmitted to the SAR layer. In the SAR layer, the data isdivided into groups of 48 bytes according to the AAL TYPE 5 protocol andtransmitted to the ATM layer. In the ATM layer, as shown in FIG. 32, anATM cell is formed by attaching the 5-byte cell header as indicated bythe hatched section of 1104.

The ATM cell block sequence is constructed of 248 ATM cell blocks, andtherefore, the protocol data unit of 1102 is processed exactly in thenumber of 248/8=31. Accordingly, there is no need for adding the dummydata (PAD) for establishing the protocol data unit, so that veryefficient transmission can be achieved.

The ATM cell forming circuit 105 a executes the processing of the AALlayer and the ATM layer. In regard to circuits for the processing,equipments for the transmission according to the AAL TYPE 5 protocol arecurrently popularized, and the circuits can be easily realized by usingthose equipments. In regard to the network interface 106, ATM physicallayer LSIs and the like are popularized, and the interface can be easilyrealized by using those equipments. Therefore, the AAL layer, the ATMlayer and the ATM physical layer can be easily achieved at low cost.

As described above, in the present preferred embodiment, a data amountreduction of 2.87% can be achieved in a similar manner to that of thefirst preferred embodiment, so that the communications load can beremarkably reduced and the use of the resources of the communicationsnetwork can be reduced. By virtue of the reduction in the amount ofcommunications, the communications time is reduced and the reliabilityof the real-time communications is improved by that much or degree.Furthermore, the load applied on the ATM network is reduced, the loadapplied on the ATM switch inside the network is reduced and theprobability of the occurrence of the cell loss is also reduced, so thatvery reliable communications with respect to errors can be achieved.Furthermore, the user information section of CS of the TYPE 5 can beeffectively used, so that transmission of a high efficiency can beachieved.

The data are delivered after the processing in the upper layer in a formfor very easy processing in the AAL layer, and therefore, the preferredembodiment can be used necessitating no additional circuit for theprocessing of the AAL layer and the subsequent stages. Furthermore, byvirtue of the execution of the processing based on the standard of theAAL TYPE 5, the currently popularized equipments can be used as theyare. The circuit to be added can be realized with a very simple circuitconstruction, and therefore, the circuit can be very easily achieved atlow cost.

Eleventh Preferred Embodiment

FIG. 33 is a block diagram showing a construction of a DIF processingcircuit 104 i according to an eleventh preferred embodiment of thepresent invention, while FIG. 34 is a block diagram showing a packetblock generating method executed by an ATM transmission apparatusprovided with the DIF data processing circuit 104 i of FIG. 33.

This eleventh preferred embodiment is characterized in that a parityadding circuit 1401, an ATM cell block sequence buffer memory 1402 andan interleave control circuit 1403 are further provided as compared withthe DIF data processing circuit 104 of FIG. 4. In this case, the parityadding circuit 1401 adds a predetermined Parity for FEC to the datastring outputted from the block buffer memory 6002 in a predeterminedunit of data, and then, outputs data to which the Parity for FEC isadded. Next, the interleave control circuit 1403 executes an interleaveprocess by writing the data outputted from the parity adding circuit1401 into the ATM cell block sequence buffer memory 1402 having a matrixform in the first direction of the matrix, and thereafter, reading thedata from the ATM cell block sequence buffer memory 1402 in the seconddirection perpendicular to the first direction of the matrix, and then,outputs the data obtained after the interleave process in a unit of datain the second direction. Further, the ATM cell forming circuit 105 a andthe network interface 106 transmit the inputted data to the ATM network100 with the data unit in the second direction used as a transmissionunit.

FIG. 34 shows the data processing of the eleventh preferred embodimentof the present invention. The eleventh preferred embodiment has theeffect that the error correction effect can be improved by executing thedata interleave and effectively utilizing the error detection by CRCexecuted by the AAL TYPE 5 protocol.

In FIG. 34, the reference numeral 1201 denotes the ATM cell blocksequence described in the first preferred embodiment. The referencenumeral 1202 denotes data obtained by subjecting the ATM cell blocksequence 1201 to an interleave process and a parity for FEC addingprocess according to a method as described later, and the hatchedsection is the Parity for FEC.

The reference numeral 1203 denotes the CS of the AAL layer. Thereference numeral 1204 denotes the data construction of the SAR sublayerof the AAL layer. The reference numeral 1205 denotes the cells of theATM layer. The processes of 1203, 1204 and 1205 are the same as thosedescribed in the fourth preferred embodiment. What is different from thefourth preferred embodiment is only the point that the amount ofinformation is increased by the Parity for FEC and the number ofprocessing times is increased.

FIG. 35 is a memory map showing storage contents of an ATM cell blocksequence buffer memory 1402 according to a packet block generatingmethod executed by the interleave control circuit 1403 of FIG. 33

According to the method shown in FIG. 35, the data write direction andread direction are shown by the conception of the two-dimensional matrixon the ATM cell block sequence buffer memory 1402. Each piece of userinformation has 376 bytes, and the data of the ATM cell block sequenceis stored into 31 pieces of user information. Therefore, the data has atotal of 376×31=11656 bytes corresponding to the data amount of the ATMcell block sequence. Accordingly, the processing can be achieved withoutincorporating dummy data, so that effective transmission can beachieved.

The writing of data into the ATM cell block sequence buffer memory 1402is executed in the column direction (longitudinal direction in thefigure) as denoted by 9001 in FIG. 35. The parity amount may have anyvalue corresponding to the required error correction capacity, and fourbytes are provided for 31-byte information in the present preferredembodiment.

A 4-byte Parity for FEC is added to the 31-byte data. When the writingin the column direction is completed up to the Parity for FEC, then thedata obtained by adding the 4-byte Parity for FEC to the next 31-bytedata is written in the column direction so that the address in the rowdirection increases. When the writing of all the data and parities forFEC is completed, then the next reading is executed.

On the other hand, the reading is executed in the direction (horizontaldirection in FIG. 35) that is two-dimensionally perpendicular to thewrite direction as shown in FIG. 35. In this case, the reading isexecuted from the user information 0, user information 1 and userinformation 2 to the Parity for FEC 3.

Furthermore, as denoted by 1203 in FIG. 34, processing of additionalinformation of CRC and so on is executed through the AAL process forevery read of the user information. On the receiver side of the ATMtransmission terminal apparatus, the error detection can be executed bythe CRC error check, allowing the loss correction to be achieved by theadded parity. Therefore, the correction capacity is increased takingadvantage of the AAL standard. It is to be noted that the correction ofup to double error can be achieved by the added parity.

In the DIF data processing circuit 104 i shown in FIG. 33, to the ATMcell block sequence outputted from the block buffer memory 6002 is addedthe 4-byte Parity for FEC by the parity adding circuit 1401 every 31bytes, and thereafter, is inputted to the ATM cell block sequence buffermemory 1402. The ATM cell block sequence buffer memory 1402 isconstructed of two memories capable of storing therein the userinformation and the Parity for FEC shown in FIG. 35 and alternately usedfor writing use and reading use. The data writing and reading of the ATMcell block sequence buffer memory 1402 are executed by the interleavecontrol circuit 1403.

The interleave control circuit 1403 generates an address so that 35-bytedata obtained by adding the 4-byte parity to the 31-byte data outputtedfrom the parity adding circuit 1401 is written into the ATM cell blocksequence buffer memory 1402 in the column direction (longitudinaldirection in FIG. 35) and executes the writing of the data. When thewriting of data into each column is completed, the writing is advancedin the column direction of the data in a direction in which the rowaddress increases, and the writing is switched to the reading when thewriting of the memory shown in FIG. 35 is completed (except for the8-byte additional information). For the reading, the interleave controlcircuit 1403 generates an address so that the data is read in the rowdirection of the matrix of FIG. 35 from the ATM cell block sequencebuffer memory 1402, thereby sequentially reading the data in a unit ofuser information (376 bytes).

The interleave control circuit 1403 repeatedly executes the generationof fixed addresses for interleave, and therefore, the circuit can beconstructed of a simple circuit with a ROM in which the addresses ofone-time sequence are stored. The data read out from the ATM cell blocksequence buffer memory 1402 is outputted from an output terminal 1404.The output from the output terminal 1404 becomes the output of the DIFdata processing circuit 104 of FIG. 1, and therefore, the nextprocessing proceeds to the ATM cell forming circuit 105 a of FIG. 1.

The ATM cell forming circuit 105 a executes the processing of the AALlayer and the ATM layer as described above. In regard to circuits forthe above processing, equipments for the transmission according to theAAL TYPE 5 protocol are currently popularized, and the circuits can beeasily realized by using those equipments. In regard to the networkinterface 106, ATM physical layer LSIs and the like are popularized, andthe interface can be easily realized by using those equipments.Therefore, the AAL layer, the ATM layer and the ATM physical layer canbe easily realized at low cost.

As described above, according to the eleventh preferred embodiment, theerror correction effect is improved by taking advantage of the result ofthe error detection of the AAL TYPE 5 based on the ATM standard andadding the Parity for FEC so that the parity becomes perpendicular tothe conceptual direction of error detection of AAL TYPE 5. Inparticular, the cell loss (packet loss) that is the error characteristicof the ATM communications (packet communications) can be detected by theerror check of the AAL TYPE 5 and the loss correction of the CS block ofwhich an error is detected can be achieved. Therefore, highly-reliablecommunications tolerant particularly of the cell loss can be achieved.

Furthermore, the interleave process is executed by the interleavecontrol circuit 1003, and therefore, the effect of dispersing errors ina unit of ATM cell block sequence is very great. Furthermore, there aremany equipments based on the ATM standard and those equipments can beutilized for the AAL processing, and therefore, the present inventioncan be easily achieved at low cost.

Furthermore, a data amount reduction of 2.87% can be achieved in asimilar manner to that of the first preferred embodiment, so that thecommunications load can be remarkably reduced and the use of theresources of the communications network can be reduced. By virtue of thereduction in the amount of communications, the communications time isreduced and the reliability of the real-time communications is improvedby that much or degree.

Furthermore, the interleave unit is made equal to the data amount of theATM cell block sequence, and therefore, the data transmission can beefficiently executed without adding the dummy data or the like.Consequently, the communications load can be remarkably reduced and theuse of the resources of the communications network can be reduced. Byvirtue of the reduction in the amount of communications, thecommunications time becomes short, thereby improving the reliability ofthe real-time communications by that much or degree.

The data are delivered after the processing in the upper layer in a formfor very easy processing in the AAL layer, and therefore, the preferredembodiment can be used necessitating no additional circuit for theprocessing of the AAL layer and the subsequent stages. That is, thecurrently popularized equipments can be used as they are, and thecircuit to be added can be realized with a very simple circuitconstruction, and therefore, the circuit can be very easily realized atlow cost. Furthermore, the error detection by CRC is executed, andtherefore, not only the cell loss but also the bit error are surelydetected, so that a high-quality transmission system free of erroneouscorrection can be provided.

Although the interleave is executed in the eleventh preferredembodiment, the scope of the present invention does not exclude the formin which no interleave is executed. In such a case, it is proper to makethe direction in which the Parity for FEC is added as in, for example,FIG. 35 is made identical to the direction of the present preferredembodiment and make the data write direction and read directionidentical to each other. Even in such a case, the effect that the cellloss correction capacity is high is not lost.

The eleventh preferred embodiment takes the case where the compressedimage is transmitted as an example. In regard to, for example,uncompressed image and sound information, the error does not propagateto every compressed packet, and the error is dispersed by the interleaveeffect, so that specially high-quality transmission can be achieved.

Twelfth Preferred Embodiment

FIG. 36 is a view showing a construction of a twelfth preferredembodiment of the present invention, wherein FIG. 36(A) is a blockdiagram showing a construction of the DIF data processing circuit 104 jof the twelfth preferred embodiment, FIG. 36(B) is a block diagramshowing data inputted from the block buffer memory 6002 to theinterleave buffer memory 2600 of FIG. 36(A), FIG. 36(C) is a memory mapshowing storage contents of the interleave buffer memory 2600 accordingto an interleave method executed by the interleave control circuit 2601of FIG. 36(A), FIG. 36(D) is a block diagram showing data inputted fromthe parity adding circuit 2602 to the interleave buffer memory 2603 ofFIG. 36(A) and FIG. 36(E) is a memory map showing storage contents ofthe interleave buffer memory 2603 according to an interleave methodexecuted by the interleave control circuit 2604 of FIG. 36(A).

This twelfth preferred embodiment is characterized in that an interleavebuffer memory 2600, an interleave control circuit 2601, a parity addingcircuit 2602, an interleave buffer memory 2603 and an interleave controlcircuit 2604 are provided in place of the circuits 1401, 1402 and 1403as compared with the DIF data processing circuit 104 i of the eleventhpreferred embodiment of FIG. 33.

The DIF data processing circuit 104 i of this twelfth preferredembodiment is provided with:

(a) an interleave control circuit 2601 that executes a first interleaveprocess by writing the data string outputted from the block buffermemory 6002 into the interleave buffer memory 2600 having a first matrixform in the first direction of the first matrix, and thereafter, readingthe data from the interleave buffer memory 2600 in the second directionperpendicular to the first direction of the first matrix, and then,outputs the data obtained after the first interleave process in a unitof data in the second direction;

(b) a parity adding circuit 2602 that adds a predetermined Parity forFEC to the data outputted from the interleave buffer memory 2600 in aunit of data in the second direction, and then, outputs the data towhich the Parity for FEC is added; and

(c) an interleave control circuit 2604 that executes a second interleaveprocess by writing the data outputted from the parity adding circuit2602 into the interleave buffer memory 2603 having a second matrix formin a fourth direction of the second matrix coinciding with the seconddirection of the first matrix, and thereafter, reading the data from theinterleave buffer memory 2603 in a third direction perpendicular to thefourth direction of the second matrix, and then, outputs the dataobtained after the second interleave process in a unit of data in thethird direction.

This twelfth preferred embodiment will be described based on the casewhere the interleave is not executed according to the system of theeleventh preferred embodiment. The present preferred embodiment willalso be described taking the case where the DIF data string 1702 of FIG.37 is transmitted as an example.

FIG. 38 is a block diagram showing a structure of data outputted fromthe ATM cell forming circuit 105 of the ATM transmission apparatusprovided with the DIF data processing circuit 104 j of FIG. 36(A). Inthe conceptual two-dimensional matrix shown in FIG. 38, the writedirection and the read direction of the DIF data string coincide witheach other. The DIF data string 1702 outputted from the block buffermemory 6002 is written in the row direction of the above matrix. The DIFdata string 1702 has 467 bytes, and therefore, 5-byte dummy data (PAD)is added through the processing of the AAL TYPE 5 for the adjustment tothe valid data length of 48 bytes of the ATM cell, and a 8-byte trailerincluding CRC and the like is added in a similar manner through theprocessing of the AAL TYPE 5 for the formation of a total of 480 bytes.Then, one PDU is transmitted with 10 ATM cells.

Finally, the DIF block data of 77 bytes is stored into the data sectionindicated by the thick lines in FIG. 38. A header is added to each DIFdata string, which becomes the header section indicated by theright-side-down hatching. Based on the AAL TYPE 5 transmission protocol,the PAD indicated by the PAD section and the trailer indicated by thetrailer section are added to the tail in the row direction of the matrixfor each DIF block data string, header and Parity for FEC.

In the twelfth preferred embodiment, five parities for FEC are added to50 PDUs for the transmission, however, the unit of addition of theParity for FEC is not limited to this.

One PDU is constructed of six DIF blocks as described with reference toFIG. 37, and the transmission unit shown in FIG. 38 is constructed of avalid data section of 50 rows, and therefore, one PDU is constructed of6×50=300 DIF blocks. One frame is constructed of 1500 DIF blocks, andtherefore, this results in 1500/300=5, so that the DVC data of one framecan be transmitted by five times the transmission unit of FIG. 38.

In FIG. 36(A), the inputting of the DIF block data string is executedvia the input terminal 6001. In FIG. 36(A), the DIF block data string1702 shown in FIG. 9 and FIG. 36(B) is obtained by the block buffermemory 6002 and the block buffer memory control circuit 6003. This datastring 1702 is the same as 1702 of FIG. 9. The interleave buffer memory2600 has a size for storing the data section and header section of FIG.38, and the data outputted from the block buffer memory 6002 issequentially written into the interleave buffer memory 2600 in the rowdirection while shifting the row from the left to the right in terms ofthe conception of the two-dimensional matrix. The data reading from theinterleave buffer memory 2600 is executed in the column direction whileshifting the column from the upside to the downside. The control ofwriting and reading of the interleave buffer memory 2600 is executed bythe interleave buffer memory control circuit 2601. These are the fixedwriting and reading methods, and therefore, the methods can be easilyimplemented by storing a program of the methods in, for example, a ROMof a small storage capacity and providing the interleave control circuit2601 with the ROM.

The structural view of the data written in the interleave buffer memory2600 is shown in FIG. 36(C). This corresponds to the data section andthe header section of FIG. 38.

The output data from the interleave buffer memory 2600 is transmitted tothe parity adding circuit 2602, and as shown in FIG. 36(D), the 5-byteParity for FEC is added to the 50-byte data conceptually in the columndirection.

The output data from the parity adding circuit 2602 is written into theinterleave buffer memory 2603. The writing is executed conceptually inthe column direction while shifting the column from the left to theright. The data reading is sequentially executed in the row directionwhile shifting the row from the upside to the downside. The write andread control of the interleave buffer memory 2603 is executed by theinterleave control circuit 2604. These are the fixed write and readmethods, and therefore, the methods can be easily achieved by storing aprogram of the methods in, for example, a ROM of a small storagecapacity and providing the interleave control circuit 2604 with the ROM.

The structural view of the data written in the interleave buffer memory2603 is shown in FIG. 36(E). This corresponds to the data section, theheader section and the error correction parity section of FIG. 38. Theoutputting from the interleave buffer memory 2603 is executed via anoutput terminal 2605.

The processing of the AAL TYPE 5 is executed in a similar manner to thedescription of the tenth preferred embodiment, whereby the ATM cellforming circuit 105 a executes addition of the PAD, addition of thetrailer of CRC and the like, and the processed ATM cell block istransmitted to the ATM network 100 via the network interface 106.

As described above, according to the twelfth preferred embodiment of thepresent invention, the error correction by CRC is executed effectivelyutilizing the AAL protocol function. Therefore, a high-qualitytransmission system free of error correction can be provided by surelydetecting not only the cell loss but also the bit error and executingthe loss correction in the upper layer.

The twelfth preferred embodiment has been described taking the casewhere the DIF data string 1702 of FIG. 9 is transmitted as an example.However, the data deletion is not the subject matter of the presentinvention, and an effect is obtained by executing error checkconceptually in one direction of the two-dimensional matrix andexecuting the error correction perpendicularly to the above direction.Therefore, the scope of the present invention does not exclude the casewhere no data deletion is executed.

Thirteenth Preferred Embodiment

FIG. 39 is a block diagram showing a construction of an ATM transmissionapparatus 1 c according to a thirteenth preferred embodiment of thepresent invention, while FIG. 40 is a block diagram showing a packetblock generating method executed by the ATM transmission apparatus 1 cof FIG. 39.

The ATM transmission apparatus 1 c of the thirteenth preferredembodiment is provided with a data processing unit 1601 and an ATMtransmission terminal unit 102. In this case, the data processing unit1601 is provided with a DIF data processing circuit 104 similar to thatof FIG. 1 and an MPEG-TS generating circuit 1603.

The thirteenth preferred embodiment is characterized by being providedwith:

(a) a DIF data processing circuit 104 that generates a transmissionheader having a new identifier by deleting predetermined redundancyinformation from block information belonging to a plurality of blocksbased on data string outputted from the encoding unit 101, and generatesa transmission unit having the generated transmission header;

(b) an MPEG-TS generating circuit 1603 that outputs the data stringincluding the transmission unit generated by the DIF data processingcircuit 104 while dividing the data string into a plurality of packetsin a unit of MPEG transport stream packets; and

(c) an ATM transmission terminal unit 102 that transmits the pluralityof packets outputted from the MPEG-TS generating circuit 1603 via atransmission line.

The thirteenth preferred embodiment provides a data transmission systemcapable of mapping the data to MPEG transport stream packets (referredto as TSP hereinafter) and easily connecting the data to the existingMPEG transmission apparatus in conformity to the standard of MPEG overATM.

The standard of MPEG over ATM is described in “The ATM Forum TechnicalCommittee Audiovisual Multimedia Service: Video on Demand Specification1.0” af-saa-0049.000 December, 1995, ATM Forum Technical Committee.

In FIG. 40, the reference numeral 1501 denotes an ATM cell blocksequence as described in the first preferred embodiment. The ATM cellblock sequence is comprised of 248 ATM cell blocks of 47 bytes. On theother hand, TSP is constructed of 188 bytes. Therefore, the ATM cellblock sequence can be exactly stored in 47×248/188=62 TSPs. That is,four ATM cell blocks are stored in the TSP. In FIG. 40, the transformfrom 1501 to 1502 shows the state.

The subsequent processing conforms to the standard of MPEG over ATM, andas denoted by 1503, the ATM transmission is executed by connecting twoMTPs together, adding additional information of the AAL TYPE 5,subsequently dividing the resultant into 48-byte cells as denoted by1504 and further adding the ATM cell header as denoted by 1505.

In the thirteenth preferred embodiment, the data amount appropriate forthe mapping to MTP, i.e., the total data amount has already been themultiple of 188 bytes at the time point of the formation of the ATM cellblock sequence 1501 (upper layer with respect to the AAL). Therefore,the subsequent data becomes very simple since the data is merelysubjected successively to the predetermined processes.

In FIG. 39, the reference numeral 1601 denotes a data processing unitfor generating an MPEG transport stream and is constructed of a DIF dataprocessing circuit 104 and an MPEG-TS generating circuit 1603. The DIFdata processing circuit 104 is the same as that of FIG. 1, i.e., thesame circuit as that of FIG. 4. The MPEG-TS generating circuit 1603forms data each having 188 bytes from four ATM cell blocks based on thedata string outputted from the DIF data processing circuit 104, andthen, outputs the MPEG transport stream. The ATM transmission terminalunit 102 has a circuit similar to that of FIG. 1 and transmits the MPEGtransport stream outputted from the MPEG-TS generating circuit 1603 tothe ATM network 100 while putting the MPEG transport stream into ATMcells. That is, the ATM transmission terminal unit 102 is a unit forexecuting the processing of the physical layers of 1503, 1504 and 1505of FIG. 40 and their lower-order layers and transmitting the resultantto the ATM network 100. The currently widely popularized equipments canbe utilized as they are, and therefore, the circuit can be simplyrealized at low cost.

As described above, according to the thirteenth preferred embodiment,the DVC data is made to have data construction appropriate for thestandard of MPEG over ATM, so that the currently widely popularized MPEGtransmission equipments can be utilized. The currently popularizedequipments can be used as they are, so that the DVC data can betransmitted in ATM with a very simple construction at low cost.

In the thirteenth preferred embodiment, a data amount reduction of 2.87%can be achieved in a similar manner to that of the first preferredembodiment, so that the communications load can be remarkably reducedand the use of the resources of the communications network can bereduced. By virtue of the reduction in the amount of communications, thecommunications time is reduced and the reliability of the real-timecommunications is improved by that much or degree.

Furthermore, the load applied on the ATM network is small and the loadapplied on the ATM switch and so on inside the network is also small.Therefore, the probability of the occurrence of cell loss or the like isremarkably reduced, so that highly-reliable transmission having a greattolerance of the error can be achieved.

Although the AAL layer processing is executed by the AAL TYPE 5 in thethirteenth preferred embodiment, the ATM cell block, which isconstructed of 47 bytes, is appropriate for the case where theprocessing is executed according to the AAL TYPE 1 protocol. Equipmentscapable of executing transmission according to the AAL TYPE 1 protocolare also currently widely popularized, and the equipments can beutilized as they are.

As described above, according to the first to thirteenth preferredembodiments of the present invention, the digitized image signal, soundsignal and additional information can be transmitted in ATM.

Although the above-mentioned preferred embodiments take the ATM as anexample of the transmitting means, the scope of the invention of thepresent application does not exclude the case where other packetcommunications are used as the transmitting means.

Although the above-mentioned preferred embodiments take the householddigital VTR data as an example, the digital VTR for the broadcastingbusiness use of the same compression system is under discussion for thestandardization. The scope of the present invention does not exclude thecase where the invention of the present application is applied to it.

Industrial Applicability

As described above, the currently popularized equipments can be used asthey are, and the additional circuit can be realized with a very simplecircuit construction. Therefore, the circuit can be realized very easilyat low cost. According to the present invention, for example, the dataof the DVC system, in which the image data, sound data and otheradditional information data are outputted in a data string obtained bydividing the data into fixed-length blocks can be transmitted by thepacket communications network of, for example, the ATM network.

The first aspect of the present invention enables the communicationswith a remarkably reduced amount of information, so that thecommunications load can be remarkably reduced and the use of theresources of the communications network can be reduced. By virtue of thereduction in the amount of communications, the communications time isreduced and the reliability of the real-time communications is improvedby that much or degree. The communications zone used by the packetcommunications network is reduced, the load applied on the network isreduced, and the load applied on the switch of the network is alsoreduced. Therefore, the probability of packet abandonment and the likeis reduced, so that highly-reliable transmission can be achieved.

According to the second aspect of the present invention, if the packetloss and bit error are within the range of error correction, then theerror is corrected by the error correction. Even when packet loss andbit error beyond the error correction capacity occur, the error does notpropagate, so that high-quality image and sound transmission having agreat tolerance of the packet loss and bit error can be provided.

According to the third aspect of the present invention, if the packetloss and bit error are within the range of error correction, then theerror is corrected by the error correction. When the packet loss and biterror beyond the error correction capacity occur, then the presence orabsence of the bit error is surely detected by the error check, so thatthe DIF blocks including no bit error are outputted as they are for theutilization of the greater part of data while treating the DIF blockincluding a bit error as an error. By thus executing the errorcorrection process, a transmission system that maintains a high imagequality and a high sound quality can be provided.

According to the fourth aspect of the present invention, if the packetloss and bit error occur, the header information such as the time codeor the like can be surely detected, so that the position of thetransmitted image information and so on can be surely detected, therebyallowing high-quality image and sound transmission to be achieved.

According to the fifth aspect of the present invention, the errordetection result based on the transmission standard of the predeterminedpacket communications network is utilized, and the Parity for FEC isattached perpendicular to the conceptual direction of error detection,thereby allowing the error correction effect to be utilized to themaximum. In particular, the packet loss that is the error characteristicof the packet communications network can be detected by the errordetection and the loss correction of the predetermined block in whichthe error is detected can be achieved. Therefore, highly-reliablecommunications particularly tolerant of the packet loss can be achieved.

According to the sixth aspect of the present invention, an advantageouseffect similar to that of the first aspect of the present invention isprovided, and, for example, digital data such as the DVC data or thelike can be made to have a data construction appropriate for thestandard of MPEG over ATM. Therefore, the currently widely popularizedMPEG transmission equipments can be utilized. The currently popularizedequipments can be used as they are, so that the digital data of, forexample, the DVC data can be transmitted by the ATM transmission with avery simple construction at low cost.

What is claimed is:
 1. A packet transmission apparatus for transmittingin a packet form a transmission unit including a data string arranged todivide predetermined data into a plurality of blocks, each block havinga fixed length, block information for specifying at least one of a blocktype and a block order being added to each block, said packettransmission apparatus comprising: generating means for generating atransmission header having a new identifier for an application layer bydeleting predetermined redundancy information from the block informationbelonging to the plurality of blocks based on the data string, andgenerating a transmission unit having the generated transmission header;and transmitting means for transmitting the transmission unit generatedby said generating means by way of a transmission line, wherein saidgenerating means is operable to generate the transmission header bydeleting the predetermined redundancy information by: retaining oneheader information among a set of a plurality of sequentially continuousheader information and deleting the other header information belongingto the set if the plurality of header information belonging to the setare generated sequentially and continuously.
 2. The packet transmissionapparatus as claimed in claim 1, wherein said generating means isoperable to generate a new identifier by making the block information ofone block represent the block information of the plurality of blocks,and to generate a transmission header having the generated identifier.3. The packet transmission apparatus as claimed in claim 2, wherein saidgenerating means is operable to make the block information of one blockrepresent the block information of an identical block.
 4. The packettransmission apparatus as claimed in claim 1, wherein said generatingmeans is operable to delete redundancy information that includes atleast one of reserved data and invalid data.
 5. The packet transmissionapparatus as claimed in claim 1, wherein said generating means isoperable to generate the transmission header to include a time code anda serial number.
 6. The packet transmission apparatus as claimed inclaim 1, wherein said transmitting means is operable to transmit thetransmission unit by an ATM transmission system using AAL TYPE 1 as anadaptation layer function of an asynchronous transfer mode.
 7. Thepacket transmission apparatus as claimed in claim 1, wherein saidtransmitting means is operable to transmit the transmission unit by anATM transmission system using AAL TYPE 5 as an adaptation layer functionof an asynchronous transfer mode.
 8. The packet transmission apparatusas claimed in claim 6, wherein said transmitting means is operable toadd a parity for error correction to the generated transmission unit,thereafter, to execute an interleave process on data including the addedparity for error correction, and to output data obtained after theinterleave process as a modified transmission unit.
 9. The packettransmission apparatus as claimed in claim 8, wherein said generatingmeans is operable to execute the interleave process by writing the dataincluding the added parity for error correction into a storage apparatusas a matrix in a first direction of the matrix, and thereafter, to readfrom the storage apparatus the data in a second direction perpendicularto the first direction of the matrix.
 10. A packet transmissionapparatus for transmitting in a packet form a transmission unitincluding a data string arranged to divide predetermined data into aplurality of blocks, each block having a fixed length, block informationfor specifying at least one of a block type and a block order beingadded to each block, comprising: generating means for generating atransmission header having a new identifier for an application layer bydeleting predetermined redundancy information from the block informationbelonging to the plurality of blocks based on the data string, andgenerating a transmission unit having the generated transmission header;packet forming means for dividing a data string including thetransmission unit generated by said generating means, into a pluralityof packets in a unit of MPG transport stream packets, and outputting theplurality of packets; and transmitting means for transmitting theplurality of packets outputted from said packet forming means by way ofa transmission line, wherein said generating means is operable togenerate the transmission header by deleting the predeterminedredundancy information by: retaining one header information among a setof a plurality of sequentially continuous header information anddeleting the other header information belonging to the set if theplurality of header information belonging to the set are generatedsequentially and continuously.